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[uart]

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- added simulation entities

git-svn-id: http://moon:8086/svn/vhdl/trunk@1079 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
jens
2015-05-14 10:59:18 +00:00
parent 4cd6758a4b
commit db9e21023c
3 changed files with 124 additions and 22 deletions
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lib/uart/uart_rx_sim.vhd
+55
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@@ -0,0 +1,55 @@
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
--
------------------------------------------------------------------------------------
--
-- Main Entity for UART_RX
--
entity uart_rx is
Port ( serial_in : in std_logic;
data_out : out std_logic_vector(7 downto 0);
read_buffer : in std_logic;
reset_buffer : in std_logic;
en_16_x_baud : in std_logic;
buffer_data_present : out std_logic;
buffer_full : out std_logic;
buffer_half_full : out std_logic;
clk : in std_logic);
end uart_rx;
--
------------------------------------------------------------------------------------
--
-- Start of Main Architecture for UART_RX
--
architecture behavior of uart_rx is
--
------------------------------------------------------------------------------------
--
-- Signals used in UART_RX
--
------------------------------------------------------------------------------------
--
--
------------------------------------------------------------------------------------
--
-- Start of UART_RX circuit description
--
------------------------------------------------------------------------------------
--
begin
data_out <= X"00";
buffer_data_present <= '0';
buffer_full <= '0';
buffer_half_full <= '0';
end behavior;
------------------------------------------------------------------------------------
--
-- END OF FILE UART_RX.VHD
--
------------------------------------------------------------------------------------
lib/uart/uart_tx_sim.vhd
+65
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@@ -0,0 +1,65 @@
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
use std.textio.all; -- Imports the standard textio package.
--
------------------------------------------------------------------------------------
--
-- Main Entity for UART_TX
--
entity uart_tx is
Port ( data_in : in std_logic_vector(7 downto 0);
write_buffer : in std_logic;
reset_buffer : in std_logic;
en_16_x_baud : in std_logic;
serial_out : out std_logic;
buffer_full : out std_logic;
buffer_half_full : out std_logic;
tx_complete : out std_logic;
tx_empty : out std_logic;
clk : in std_logic);
end uart_tx;
------------------------------------------------------------------------------------
--
-- Start of UART_TX circuit description
--
------------------------------------------------------------------------------------
--
ARCHITECTURE behavior OF uart_tx IS
begin
serial_out <= '0';
buffer_full <= '0';
buffer_half_full <= '0';
tx_complete <= '1';
tx_empty <= '1';
registers_write:
process(clk)
file output: text open write_mode is "STD_OUTPUT";
variable L : line;
begin
if rising_edge(clk) then
if write_buffer = '1' then
if data_in /= X"0D" then
write(L, character'val(to_integer(unsigned(data_in))));
end if;
if data_in = X"0A" then
writeline(output, L);
end if;
end if;
end if;
end process;
end behavior;
------------------------------------------------------------------------------------
--
-- END OF FILE UART_TX.VHD
--
------------------------------------------------------------------------------------
lib/uart/uart_wb.vhd
+4 -22
View File
@@ -1,13 +1,8 @@
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
use std.textio.all; -- Imports the standard textio package.
ENTITY uart_wb IS
Generic
(
simulate_tx : boolean := false
);
Port
(
CLK_I : in STD_LOGIC;
@@ -91,8 +86,6 @@ begin
------------------------------------------------------------------
registers_write:
process(CLK_I)
file output: text open write_mode is "STD_OUTPUT";
variable L : line;
begin
if rising_edge(CLK_I) then
reg_we_uart_tx <= '0';
@@ -105,16 +98,7 @@ registers_write:
when "0000" =>
reg_uart_tx <= DAT_I(7 downto 0);
if simulate_tx then
if DAT_I(7 downto 0) /= X"0D" then
write(L, character'val(to_integer(DAT_I(7 downto 0))));
end if;
if DAT_I(7 downto 0) = X"0A" then
writeline(output, L);
end if;
else
reg_we_uart_tx <= '1';
end if;
reg_we_uart_tx <= '1';
when "0001" =>
rx_int_en <= DAT_I(6);
@@ -181,7 +165,7 @@ irq_register:
end if;
end process;
inst_uart_tx: uart_tx
inst_uart_tx: entity work.uart_tx
port map
(
data_in => std_logic_vector(reg_uart_tx),
@@ -196,7 +180,7 @@ inst_uart_tx: uart_tx
clk => CLK_I
);
inst_uart_rx: uart_rx
inst_uart_rx: entity work.uart_rx
port map
(
serial_in => ser_rx,
@@ -210,9 +194,7 @@ inst_uart_rx: uart_rx
clk => CLK_I
);
status_sim <= "0000000000000000";
status_real <= "000000" & irq_rx & irq_tx & '0' & rx_int_en & tx_int_en & rx_data_present & rx_full & rx_half_full & tx_full & tx_half_full ;
uart_status_port <= status_sim when simulate_tx else status_real;
uart_status_port <= "000000" & irq_rx & irq_tx & '0' & rx_int_en & tx_int_en & rx_data_present & rx_full & rx_half_full & tx_full & tx_half_full ;
INT_O <= irq_rx or irq_tx;