diff --git a/lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_frontend_wb.vhd b/lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_frontend_wb.vhd
index 30a1007..e078ede 100644
--- a/lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_frontend_wb.vhd
+++ b/lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_frontend_wb.vhd
@@ -253,6 +253,8 @@ begin
    
 ------------------------------------------------------------------------------------------
 	SRDY_O				<= rdy;
+	ACK_O				<= not (read_fifo_empty);
+	DAT_O				<= read_fifo_data_out;
 	rdy					<= not (cat_fifo_full or write_fifo_full or read_fifo_full) and CYC_I;
 	write_fifo_we 		<= STB_I and WE_I and rdy;
 	write_fifo_data_in	<= DAT_I;
@@ -278,16 +280,4 @@ begin
 	read_fifo_data_in	<= u_data_r(31 downto 0);	
 	read_fifo_dm_in		<= u_dm_rd_out(3 downto 0);
 
-data_register:
-	process(CLK_I)
-	begin
-		if rising_edge(CLK_I) then
-			ACK_O		<= '0';
-			if MRDY_I = '1' then
-				ACK_O		<= write_fifo_we or (CYC_I and not (WE_I or read_fifo_empty));
-				DAT_O		<= read_fifo_data_out;
-			end if;
-		end if;
-	end process;
-	
 end architecture struct;
diff --git a/lib/misc/async_port.vhd b/lib/misc/async_port.vhd
index 798697e..f61aa2f 100644
--- a/lib/misc/async_port.vhd
+++ b/lib/misc/async_port.vhd
@@ -1,5 +1,5 @@
 -----------------------------------------------------------------------
--- $Header: /tmp/cvsroot/VHDL/lib/misc/async_port.vhd,v 1.1 2008-09-21 08:25:59 Jens Exp $
+-- $Header: /tmp/cvsroot/VHDL/lib/misc/async_port.vhd,v 1.2 2008-10-10 21:25:17 Jens Exp $
 -----------------------------------------------------------------------
 library IEEE;
 use IEEE.STD_LOGIC_1164.ALL;
@@ -141,11 +141,11 @@ architecture Behavioral of async_port is
 			as.cs		<= '1';
 			as.rd		<= '1';
 			if cycle_cnt = 0 then
-				cpu_vld	<= '1';
 				cc_rst			<= '1';
 				cycle_reload	<= async_timespec.ncyc_cs_hold-1;
 				as.rd			<= '0';
 				sn				<= leadout_rd;
+				cpu_vld			<= '1';
 			end if;
 				
 		when write =>
@@ -157,6 +157,7 @@ architecture Behavioral of async_port is
 				cc_rst			<= '1';
 				cycle_reload	<= async_timespec.ncyc_cs_hold-1;
 				sn				<= leadout_wr;
+				cpu_vld			<= '1';
 			end if;
 
 		when leadout_rd =>