From daf5a557881b845025649969590cc1029ab72da6 Mon Sep 17 00:00:00 2001 From: Jens Ahrensfeld Date: Mon, 27 May 2013 11:16:30 +0000 Subject: [PATCH] -separate write FIFO Committed on the Free edition of March Hare Software CVSNT Server. Upgrade to CVS Suite for more features and support: http://march-hare.com/cvsnt/ git-svn-id: http://moon:8086/svn/vhdl/trunk@970 cc03376c-175c-47c8-b038-4cd826a8556b --- lib/JBUS/sim/tb_busmaster_sync.fdo | 1 + lib/JBUS/sim/tb_busmaster_sync.wdo | 77 +++++++-------- lib/JBUS/src/busmaster_sync.vhd | 151 ++++++++++++++++++----------- lib/JBUS/src/tb_busmaster_sync.vhd | 97 +++++++++--------- 4 files changed, 180 insertions(+), 146 deletions(-) diff --git a/lib/JBUS/sim/tb_busmaster_sync.fdo b/lib/JBUS/sim/tb_busmaster_sync.fdo index bfaaf0f..00e228b 100644 --- a/lib/JBUS/sim/tb_busmaster_sync.fdo +++ b/lib/JBUS/sim/tb_busmaster_sync.fdo @@ -8,6 +8,7 @@ vcom -explicit -93 "../../rams/dpram_1w1r2c_ro_sim.vhd" vcom -explicit -93 "../../FIFO/src/fifo_ctrl_pkg.vhd" vcom -explicit -93 "../../FIFO/src/fifo_sync_ctrl.vhd" vcom -explicit -93 "../../FIFO/src/fifo_sync.vhd" +vcom -explicit -93 "../src/busmaster_types.vhd" vcom -explicit -93 "../src/busmaster_sync.vhd" vcom -explicit -93 "../src/tb_busmaster_sync.vhd" vsim -t 1ps -lib work tb_busmaster_sync diff --git a/lib/JBUS/sim/tb_busmaster_sync.wdo b/lib/JBUS/sim/tb_busmaster_sync.wdo index 3419731..e6e10cc 100644 --- a/lib/JBUS/sim/tb_busmaster_sync.wdo +++ b/lib/JBUS/sim/tb_busmaster_sync.wdo @@ -1,50 +1,43 @@ onerror {resume} quietly WaveActivateNextPane {} 0 -add wave -noupdate -format Logic /tb_busmaster_sync/inst_busmaster_sync/clk -add wave -noupdate -format Logic /tb_busmaster_sync/inst_busmaster_sync/rst -add wave -noupdate -format Literal -radix hexadecimal /tb_busmaster_sync/read_reg -add wave -noupdate -format Literal /tb_busmaster_sync/state +add wave -noupdate -format Logic /tb_busmaster_sync/inst_uut/clk +add wave -noupdate -format Logic /tb_busmaster_sync/inst_uut/rst add wave -noupdate -divider J-BUS -add wave -noupdate -format Logic /tb_busmaster_sync/inst_busmaster_sync/ack_i -add wave -noupdate -format Logic /tb_busmaster_sync/inst_busmaster_sync/srdy_i -add wave -noupdate -format Literal -radix hexadecimal /tb_busmaster_sync/inst_busmaster_sync/mdat_i -add wave -noupdate -format Literal -radix hexadecimal /tb_busmaster_sync/inst_busmaster_sync/mdat_o -add wave -noupdate -format Literal -radix hexadecimal /tb_busmaster_sync/inst_busmaster_sync/addr_o -add wave -noupdate -format Literal /tb_busmaster_sync/inst_busmaster_sync/sel_o -add wave -noupdate -format Logic /tb_busmaster_sync/inst_busmaster_sync/we_o -add wave -noupdate -format Logic /tb_busmaster_sync/inst_busmaster_sync/cyc_o -add wave -noupdate -format Logic /tb_busmaster_sync/inst_busmaster_sync/stb_o -add wave -noupdate -format Logic /tb_busmaster_sync/inst_busmaster_sync/mrdy_o +add wave -noupdate -format Logic /tb_busmaster_sync/inst_uut/clk +add wave -noupdate -format Logic /tb_busmaster_sync/inst_uut/rst +add wave -noupdate -format Logic /tb_busmaster_sync/inst_uut/ack_i +add wave -noupdate -format Logic /tb_busmaster_sync/inst_uut/srdy_i +add wave -noupdate -format Literal -radix hexadecimal /tb_busmaster_sync/inst_uut/mdat_i +add wave -noupdate -format Literal -radix hexadecimal /tb_busmaster_sync/inst_uut/mdat_o +add wave -noupdate -format Literal -radix hexadecimal /tb_busmaster_sync/inst_uut/addr_o +add wave -noupdate -format Literal /tb_busmaster_sync/inst_uut/sel_o +add wave -noupdate -format Logic /tb_busmaster_sync/inst_uut/we_o +add wave -noupdate -format Logic /tb_busmaster_sync/inst_uut/cyc_o +add wave -noupdate -format Logic /tb_busmaster_sync/inst_uut/stb_o +add wave -noupdate -format Logic /tb_busmaster_sync/inst_uut/mrdy_o add wave -noupdate -divider Busmaster -add wave -noupdate -format Logic /tb_busmaster_sync/inst_busmaster_sync/cycle_busy -add wave -noupdate -format Logic /tb_busmaster_sync/inst_busmaster_sync/cmd_cycle_finished -add wave -noupdate -format Logic /tb_busmaster_sync/inst_busmaster_sync/cmd_cycle_en -add wave -noupdate -format Logic /tb_busmaster_sync/inst_busmaster_sync/cmd_rdy -add wave -noupdate -format Logic /tb_busmaster_sync/inst_busmaster_sync/cmd_we -add wave -noupdate -format Literal -radix hexadecimal /tb_busmaster_sync/inst_busmaster_sync/cmd_din -add wave -noupdate -format Literal -radix hexadecimal /tb_busmaster_sync/inst_busmaster_sync/cmd_addr -add wave -noupdate -format Literal /tb_busmaster_sync/inst_busmaster_sync/cmd_sel -add wave -noupdate -format Logic /tb_busmaster_sync/inst_busmaster_sync/cmd_rw -add wave -noupdate -format Literal -radix hexadecimal /tb_busmaster_sync/inst_busmaster_sync/cmd_dout -add wave -noupdate -format Logic /tb_busmaster_sync/inst_busmaster_sync/cmd_dout_vld -add wave -noupdate -format Logic /tb_busmaster_sync/inst_busmaster_sync/cmd_dout_re -add wave -noupdate -format Literal -radix hexadecimal /tb_busmaster_sync/inst_busmaster_sync/busout_fifo_din -add wave -noupdate -format Literal -radix hexadecimal /tb_busmaster_sync/inst_busmaster_sync/busout_fifo_dout -add wave -noupdate -format Logic /tb_busmaster_sync/inst_busmaster_sync/busout_fifo_re -add wave -noupdate -format Logic /tb_busmaster_sync/inst_busmaster_sync/busout_fifo_we -add wave -noupdate -format Logic /tb_busmaster_sync/inst_busmaster_sync/busout_fifo_full -add wave -noupdate -format Logic /tb_busmaster_sync/inst_busmaster_sync/busout_fifo_empty -add wave -noupdate -format Logic /tb_busmaster_sync/inst_busmaster_sync/busin_fifo_re -add wave -noupdate -format Logic /tb_busmaster_sync/inst_busmaster_sync/busin_fifo_we -add wave -noupdate -format Logic /tb_busmaster_sync/inst_busmaster_sync/busin_fifo_full -add wave -noupdate -format Logic /tb_busmaster_sync/inst_busmaster_sync/busin_fifo_empty -add wave -noupdate -format Logic /tb_busmaster_sync/inst_busmaster_sync/cmd_en -add wave -noupdate -format Logic /tb_busmaster_sync/inst_busmaster_sync/cmd_read_en -add wave -noupdate -format Literal /tb_busmaster_sync/inst_busmaster_sync/read_cnt +add wave -noupdate -format Logic /tb_busmaster_sync/inst_uut/clk +add wave -noupdate -format Logic /tb_busmaster_sync/inst_uut/rst +add wave -noupdate -format Logic /tb_busmaster_sync/inst_uut/cmd_cycle_finished +add wave -noupdate -format Logic /tb_busmaster_sync/inst_uut/cmd_cycle_en +add wave -noupdate -format Logic /tb_busmaster_sync/inst_uut/cmd_rdy +add wave -noupdate -format Logic /tb_busmaster_sync/inst_uut/cmd_we +add wave -noupdate -format Literal -radix hexadecimal -expand /tb_busmaster_sync/inst_uut/cmd_in +add wave -noupdate -format Literal -radix hexadecimal /tb_busmaster_sync/inst_uut/dout +add wave -noupdate -format Logic /tb_busmaster_sync/inst_uut/dout_vld +add wave -noupdate -format Logic /tb_busmaster_sync/inst_uut/dout_re +add wave -noupdate -format Logic /tb_busmaster_sync/inst_uut/cycle_busy +add wave -noupdate -format Logic /tb_busmaster_sync/inst_uut/cmd_en +add wave -noupdate -format Logic /tb_busmaster_sync/inst_uut/cmd_read_en +add wave -noupdate -format Literal /tb_busmaster_sync/inst_uut/read_cnt add wave -noupdate -divider RAM -add wave -noupdate -format Literal -radix hexadecimal -expand /tb_busmaster_sync/ram64 +add wave -noupdate -format Logic /tb_busmaster_sync/inst_uut/clk +add wave -noupdate -format Logic /tb_busmaster_sync/inst_uut/rst +add wave -noupdate -format Literal /tb_busmaster_sync/state +add wave -noupdate -format Literal -radix hexadecimal /tb_busmaster_sync/read_reg +add wave -noupdate -format Literal -radix hexadecimal /tb_busmaster_sync/ram64 TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 1} {19057675 ps} 0} +WaveRestoreCursors {{Cursor 1} {7559494 ps} 0} configure wave -namecolwidth 150 configure wave -valuecolwidth 100 configure wave -justifyvalue left @@ -58,4 +51,4 @@ configure wave -gridperiod 1 configure wave -griddelta 40 configure wave -timeline 0 update -WaveRestoreZoom {0 ps} {21 us} +WaveRestoreZoom {50 ns} {21050 ns} diff --git a/lib/JBUS/src/busmaster_sync.vhd b/lib/JBUS/src/busmaster_sync.vhd index a9a7b78..148a808 100644 --- a/lib/JBUS/src/busmaster_sync.vhd +++ b/lib/JBUS/src/busmaster_sync.vhd @@ -1,11 +1,12 @@ ----------------------------------------------------------------------- --- $Header: /tmp/cvsroot/VHDL/lib/JBUS/src/busmaster_sync.vhd,v 1.1 2013-05-25 16:55:29 jens Exp $ +-- $Header: /tmp/cvsroot/VHDL/lib/JBUS/src/busmaster_sync.vhd,v 1.2 2013-05-27 11:16:22 jens Exp $ ----------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; use work.utils_pkg.all; +use work.busmaster_types.all; ------------------------------------------------------------------ entity busmaster_sync is @@ -23,14 +24,16 @@ entity busmaster_sync is cmd_cycle_en : in std_logic; cmd_rdy : out std_logic; cmd_we : in std_logic; - cmd_din : in unsigned(DATA_WIDTH-1 downto 0); - cmd_addr : in unsigned(31 downto 0); - cmd_sel : in unsigned(DATA_WIDTH/8-1 downto 0); - cmd_rw : in std_logic; - cmd_dout : out unsigned(DATA_WIDTH-1 downto 0); - cmd_dout_vld : out std_logic; - cmd_dout_re : in std_logic; + cmd_in : in bm_cmd_t; + + din : in unsigned(DATA_WIDTH-1 downto 0); + din_rdy : out std_logic; + din_we : in std_logic; + + dout : out unsigned(DATA_WIDTH-1 downto 0); + dout_vld : out std_logic; + dout_re : in std_logic; -- J-BUS signals ACK_I : in std_logic; @@ -38,7 +41,7 @@ entity busmaster_sync is MDAT_I : in unsigned(DATA_WIDTH-1 downto 0); MDAT_O : out unsigned(DATA_WIDTH-1 downto 0); ADDR_O : out unsigned(31 downto 0); - SEL_O : out unsigned(DATA_WIDTH/8-1 downto 0); + SEL_O : out unsigned(3 downto 0); WE_O : out std_logic; CYC_O : out std_logic; STB_O : out std_logic; @@ -48,47 +51,55 @@ entity busmaster_sync is architecture Behavioral of busmaster_sync is - -- Bus output FIFO - signal busout_fifo_din : unsigned(DATA_WIDTH+32+DATA_WIDTH/8+1-1 downto 0); - signal busout_fifo_dout : unsigned(DATA_WIDTH+32+DATA_WIDTH/8+1-1 downto 0); - signal busout_fifo_re : std_logic; - signal busout_fifo_we : std_logic; - signal busout_fifo_full : std_logic; - signal busout_fifo_empty : std_logic; + -- Bus Command FIFO + signal cmd_fifo_din : unsigned(32+DATA_WIDTH/8+1-1 downto 0); + signal cmd_fifo_dout : unsigned(32+DATA_WIDTH/8+1-1 downto 0); + signal cmd_fifo_re : std_logic; + signal cmd_fifo_we : std_logic; + signal cmd_fifo_full : std_logic; + signal cmd_fifo_empty : std_logic; - -- Bus input FIFO - signal busin_fifo_re : std_logic; - signal busin_fifo_we : std_logic; - signal busin_fifo_full : std_logic; - signal busin_fifo_empty : std_logic; - signal cycle_busy : std_logic; - signal cmd_en : std_logic; - signal cmd_read_en : std_logic; - signal read_cnt : integer range 0 to 65535; + -- Bus Read FIFO + signal read_fifo_re : std_logic; + signal read_fifo_we : std_logic; + signal read_fifo_full : std_logic; + signal read_fifo_empty : std_logic; + signal write_fifo_re : std_logic; + signal write_fifo_we : std_logic; + signal write_fifo_full : std_logic; + signal write_fifo_empty : std_logic; + signal cycle_busy : std_logic; + signal cmd_en : std_logic; + signal cmd_read_en : std_logic; + signal read_cnt : integer range 0 to 65535; + signal write : std_logic; begin - cmd_en <= cmd_cycle_en and cmd_we and not busout_fifo_full; - cmd_read_en <= cmd_en and not cmd_rw; + cmd_en <= cmd_cycle_en and cmd_we and not cmd_fifo_full; + cmd_read_en <= cmd_en and not cmd_in.rw; + write <= cmd_fifo_dout(32+DATA_WIDTH/8); - cmd_dout_vld <= not busin_fifo_empty; - MRDY_O <= not busin_fifo_full; - busin_fifo_we <= ACK_I and cycle_busy; - busin_fifo_re <= cmd_dout_re; - ADDR_O <= busout_fifo_dout(31 downto 0); - MDAT_O <= busout_fifo_dout(DATA_WIDTH+32-1 downto 32); - SEL_O <= busout_fifo_dout(DATA_WIDTH+32+DATA_WIDTH/8-1 downto DATA_WIDTH+32); - WE_O <= busout_fifo_dout(DATA_WIDTH+32+DATA_WIDTH/8); + dout_vld <= not read_fifo_empty; + MRDY_O <= not read_fifo_full; + read_fifo_we <= ACK_I and cycle_busy; + read_fifo_re <= dout_re; + ADDR_O <= cmd_fifo_dout(31 downto 0); + SEL_O <= cmd_fifo_dout(32+DATA_WIDTH/8-1 downto 32); + WE_O <= write; - busout_fifo_din <= cmd_rw & cmd_sel & cmd_din & cmd_addr; + cmd_fifo_din <= cmd_in.rw & cmd_in.sel & cmd_in.addr; - cmd_rdy <= not busout_fifo_full; + cmd_rdy <= not cmd_fifo_full; - busout_fifo_we <= cmd_en; - busout_fifo_re <= SRDY_I and cycle_busy; + cmd_fifo_we <= cmd_en; + cmd_fifo_re <= SRDY_I and cycle_busy; + din_rdy <= not write_fifo_full; + write_fifo_we <= din_we; + write_fifo_re <= SRDY_I and cycle_busy and write and not cmd_fifo_empty; - STB_O <= not busout_fifo_empty; + STB_O <= not cmd_fifo_empty; CYC_O <= cycle_busy; cmd_cycle_finished <= not cycle_busy; @@ -98,9 +109,9 @@ proc_bus_read_counter: if rising_edge(clk) then if rst = '1' then read_cnt <= 0; - elsif cmd_read_en = '1' and busin_fifo_we = '0' then + elsif cmd_read_en = '1' and read_fifo_we = '0' then read_cnt <= read_cnt + 1; - elsif cmd_read_en = '0' and busin_fifo_we = '1' then + elsif cmd_read_en = '0' and read_fifo_we = '1' then read_cnt <= read_cnt - 1; end if; end if; @@ -116,14 +127,14 @@ proc_cycle_busy: if cmd_we = '1' then cycle_busy <= '1'; end if; - elsif read_cnt = 0 and busout_fifo_empty = '1' then + elsif read_cnt = 0 and cmd_fifo_empty = '1' then cycle_busy <= '0'; end if; end if; end process; --- Bus input FIFO -inst_BM_IN_FIFO: entity work.fifo_sync +-- Bus READ FIFO +inst_BM_READ_FIFO: entity work.fifo_sync GENERIC MAP ( addr_width => NextExpBaseTwo(FIFO_DEPTH), @@ -134,36 +145,58 @@ inst_BM_IN_FIFO: entity work.fifo_sync ( rst => rst, clk => clk, - we => busin_fifo_we, - re => busin_fifo_re, - fifo_full => busin_fifo_full, - fifo_empty => busin_fifo_empty, + we => read_fifo_we, + re => read_fifo_re, + fifo_full => read_fifo_full, + fifo_empty => read_fifo_empty, fifo_afull => open, fifo_aempty => open, data_w => MDAT_I, - data_r => cmd_dout + data_r => dout ); --- Bus output FIFO -inst_BM_OUT_FIFO: entity work.fifo_sync +-- Bus WRITE FIFO +inst_BM_WRITE_FIFO: entity work.fifo_sync GENERIC MAP ( addr_width => NextExpBaseTwo(FIFO_DEPTH), - data_width => busout_fifo_din'length, + data_width => DATA_WIDTH, do_last_read_update => false ) PORT MAP ( rst => rst, clk => clk, - we => busout_fifo_we, - re => busout_fifo_re, - fifo_full => busout_fifo_full, - fifo_empty => busout_fifo_empty, + we => write_fifo_we, + re => write_fifo_re, + fifo_full => write_fifo_full, + fifo_empty => write_fifo_empty, fifo_afull => open, fifo_aempty => open, - data_w => busout_fifo_din, - data_r => busout_fifo_dout + data_w => din, + data_r => MDAT_O + ); + +-- Bus command FIFO +inst_BM_CMD_FIFO: entity work.fifo_sync + GENERIC MAP + ( + addr_width => NextExpBaseTwo(FIFO_DEPTH), + data_width => cmd_fifo_din'length, + do_last_read_update => false + ) + PORT MAP + ( + rst => rst, + clk => clk, + we => cmd_fifo_we, + re => cmd_fifo_re, + fifo_full => cmd_fifo_full, + fifo_empty => cmd_fifo_empty, + fifo_afull => open, + fifo_aempty => open, + data_w => cmd_fifo_din, + data_r => cmd_fifo_dout ); end Behavioral; diff --git a/lib/JBUS/src/tb_busmaster_sync.vhd b/lib/JBUS/src/tb_busmaster_sync.vhd index 0e2ac69..2301d2b 100644 --- a/lib/JBUS/src/tb_busmaster_sync.vhd +++ b/lib/JBUS/src/tb_busmaster_sync.vhd @@ -1,11 +1,12 @@ ----------------------------------------------------------------------- --- $Header: /tmp/cvsroot/VHDL/lib/JBUS/src/tb_busmaster_sync.vhd,v 1.1 2013-05-25 16:55:29 jens Exp $ +-- $Header: /tmp/cvsroot/VHDL/lib/JBUS/src/tb_busmaster_sync.vhd,v 1.2 2013-05-27 11:16:22 jens Exp $ ----------------------------------------------------------------------- LIBRARY ieee; use IEEE.STD_LOGIC_1164.ALL; USE ieee.numeric_std.ALL; +use work.busmaster_types.all; ENTITY tb_busmaster_sync IS END tb_busmaster_sync; @@ -27,23 +28,26 @@ ARCHITECTURE behavior OF tb_busmaster_sync IS signal MRDY_O : std_logic := '1'; signal SRDY_I : std_logic := '0'; signal ADDR_O : unsigned(31 downto 0) := (others => '-'); - signal MDAT_I_32 : unsigned(31 downto 0) := (others => '-'); - signal MDAT_O_32 : unsigned(31 downto 0) := (others => '-'); - signal MDAT_I : unsigned(63 downto 0) := (others => '-'); - signal MDAT_O : unsigned(63 downto 0) := (others => '-'); + signal MDAT_I_64 : unsigned(63 downto 0) := (others => '-'); + signal MDAT_O_64 : unsigned(63 downto 0) := (others => '-'); + + signal MDAT_I : unsigned(31 downto 0) := (others => '-'); + signal MDAT_O : unsigned(31 downto 0) := (others => '-'); signal cmd_cycle_finished : std_logic; signal cmd_cycle_en : std_logic := '0'; signal cmd_rdy : std_logic; signal cmd_we : std_logic := '0'; - signal cmd_din : unsigned(DATA_WIDTH-1 downto 0) := (others => '-'); - signal cmd_addr : unsigned(31 downto 0) := (others => '-'); - signal cmd_sel : unsigned(DATA_WIDTH/8-1 downto 0) := (others => '-'); - signal cmd_rw : std_logic := '0'; + + signal cmd_in : bm_cmd_t; - signal cmd_dout : unsigned(DATA_WIDTH-1 downto 0); - signal cmd_dout_vld : std_logic; - signal cmd_dout_re : std_logic := '0'; + signal din : unsigned(31 downto 0) := (others => '-'); + signal din_rdy : std_logic; + signal din_we : std_logic := '0'; + + signal dout : unsigned(31 downto 0); + signal dout_vld : std_logic; + signal dout_re : std_logic := '0'; signal rdy : std_logic := '0'; signal read_reg : unsigned(31 downto 0) := (others => '-'); @@ -196,14 +200,14 @@ ARCHITECTURE behavior OF tb_busmaster_sync IS BEGIN - MDAT_I_32 <= MDAT_I(31 downto 0); - MDAT_O <= MDAT_O_32 & MDAT_O_32; - -inst_busmaster_sync : entity work.busmaster_sync + MDAT_I <= MDAT_I_64(31 downto 0); + MDAT_O_64 <= MDAT_O & MDAT_O; + +inst_uut : entity work.busmaster_sync GENERIC MAP ( - FIFO_DEPTH => 4, - DATA_WIDTH => DATA_WIDTH + DATA_WIDTH => 32, + FIFO_DEPTH => 4 ) PORT MAP ( @@ -215,14 +219,15 @@ inst_busmaster_sync : entity work.busmaster_sync cmd_cycle_en => cmd_cycle_en, cmd_rdy => cmd_rdy, cmd_we => cmd_we, - cmd_din => cmd_din, - cmd_addr => cmd_addr, - cmd_sel => cmd_sel, - cmd_rw => cmd_rw, + cmd_in => cmd_in, - cmd_dout => cmd_dout, - cmd_dout_vld => cmd_dout_vld, - cmd_dout_re => cmd_dout_re, + din => din, + din_rdy => din_rdy, + din_we => din_we, + + dout => dout, + dout_vld => dout_vld, + dout_re => dout_re, -- JBUS Master signals CYC_O => CYC_O, @@ -233,8 +238,8 @@ inst_busmaster_sync : entity work.busmaster_sync SRDY_I => SRDY_I, MRDY_O => MRDY_O, ADDR_O => ADDR_O, - MDAT_I => MDAT_I_32, - MDAT_O => MDAT_O_32 + MDAT_I => MDAT_I, + MDAT_O => MDAT_O ); rdy_GEN: process @@ -275,24 +280,24 @@ CLK_GEN: process ram_data := (others => '-'); if ADDR_O(2) = '0' then if SEL_O = "11111111" then - ram64(to_integer(ADDR_O(31 downto 3))) <= MDAT_O; + ram64(to_integer(ADDR_O(31 downto 3))) <= MDAT_O_64; elsif SEL_O = "00001111" then - ram64(to_integer(ADDR_O(31 downto 3))) <= ram_data(63 downto 32) & MDAT_O(31 downto 0); + ram64(to_integer(ADDR_O(31 downto 3))) <= ram_data(63 downto 32) & MDAT_O_64(31 downto 0); elsif SEL_O = "11110000" then - ram64(to_integer(ADDR_O(31 downto 3))) <= MDAT_O(63 downto 32) & ram_data(31 downto 0); + ram64(to_integer(ADDR_O(31 downto 3))) <= MDAT_O_64(63 downto 32) & ram_data(31 downto 0); end if; else if SEL_O = "11111111" then - ram64(to_integer(ADDR_O(31 downto 3))) <= MDAT_O(31 downto 0) & MDAT_O(63 downto 32); + ram64(to_integer(ADDR_O(31 downto 3))) <= MDAT_O_64(31 downto 0) & MDAT_O_64(63 downto 32); elsif SEL_O = "00001111" then - ram64(to_integer(ADDR_O(31 downto 3))) <= MDAT_O(31 downto 0) & ram_data(31 downto 0); + ram64(to_integer(ADDR_O(31 downto 3))) <= MDAT_O_64(31 downto 0) & ram_data(31 downto 0); elsif SEL_O = "11110000" then - ram64(to_integer(ADDR_O(31 downto 3))) <= ram_data(63 downto 32) & MDAT_O(63 downto 32); + ram64(to_integer(ADDR_O(31 downto 3))) <= ram_data(63 downto 32) & MDAT_O_64(63 downto 32); end if; end if; end if; end if; - MDAT_I <= res; + MDAT_I_64 <= res; end if; end if; end process; @@ -302,12 +307,12 @@ CLK_GEN: process if rising_edge(CLK_O) then if RST_O = '1' then read_reg <= X"00000000"; - elsif cmd_dout_vld = '1' then - read_reg <= cmd_dout; + elsif dout_vld = '1' then + read_reg <= dout; end if; end if; end process; - cmd_dout_re <= cmd_dout_vld; + dout_re <= dout_vld; -- Master STIMULUS: process @@ -317,23 +322,25 @@ STIMULUS: process procedure cmd_write_single(addr, sel, data : unsigned) is begin - cmd_rw <= '1'; - cmd_sel <= sel; - cmd_addr <= addr; - cmd_din <= data; + din <= data; + din_we <= '1'; + + cmd_in.rw <= '1'; + cmd_in.sel <= sel; + cmd_in.addr <= addr; cmd_we <= '1'; wait until rising_edge(CLK_O) and cmd_rdy = '1'; cmd_we <= '0'; + din_we <= '0'; end procedure cmd_write_single; procedure cmd_read_single(addr : unsigned) is begin - cmd_rw <= '0'; - cmd_sel <= (others => '0'); - cmd_addr <= addr; - cmd_din <= (others => '0'); + cmd_in.rw <= '0'; + cmd_in.sel <= (others => '0'); + cmd_in.addr <= addr; cmd_we <= '1'; wait until rising_edge(CLK_O) and cmd_rdy = '1'; cmd_we <= '0';