diff --git a/lib/radio/nco/sim/tb_nco_cordic.fdo b/lib/radio/nco/sim/tb_nco_cordic.fdo
index 521ee44..ce28316 100644
--- a/lib/radio/nco/sim/tb_nco_cordic.fdo
+++ b/lib/radio/nco/sim/tb_nco_cordic.fdo
@@ -8,7 +8,7 @@ vcom -explicit  -93 "../../cordic/src/cordic_pipe_pre.vhd"
 vcom -explicit  -93 "../../cordic/src/cordic_pipe_post.vhd"
 vcom -explicit  -93 "../../cordic/src/cordic_pipe_top.vhd"
 vcom -explicit  -93 "../src/nco_pkg.vhd"
-vcom -explicit  -93 "../src/nco_cordic_dbg.vhd"
+vcom -explicit  -93 "../src/nco_cordic.vhd"
 vcom -explicit  -93 "../src/tb_nco_cordic.vhd"
 vsim -t 1ps   -lib work tb_nco
 do {tb_nco_cordic.wdo}
diff --git a/lib/radio/nco/src/tb_nco_cordic.vhd b/lib/radio/nco/src/tb_nco_cordic.vhd
index 2cac587..78b31de 100644
--- a/lib/radio/nco/src/tb_nco_cordic.vhd
+++ b/lib/radio/nco/src/tb_nco_cordic.vhd
@@ -52,8 +52,7 @@ ARCHITECTURE behavior OF tb_nco IS
 		phase_out	: out unsigned(nbits_phase-1 downto 0);
 		wave_out_i	: out sfixed;
 		wave_out_q	: out sfixed;
-		out_valid	: out std_logic;
-		debug_out	: out debug_out_t
+		out_valid	: out std_logic
 	);
 	END COMPONENT;
 
@@ -82,7 +81,6 @@ ARCHITECTURE behavior OF tb_nco IS
 	SIGNAL wave_out_q  : sfixed(sproto(nbits_wave, nbits_wave_frac)'high downto sproto(nbits_wave, nbits_wave_frac)'low);
 	SIGNAL out_valid   : std_logic;
 	SIGNAL phase_out   : unsigned(nbits_phase-1 downto 0);
-	SIGNAL debug_out   : debug_out_t;
 	
 	SIGNAL fileout_enable   : std_logic := '0';
 
@@ -109,8 +107,7 @@ BEGIN
 		phase_out	=> phase_out,
 		wave_out_i	=> wave_out_i,
 		wave_out_q	=> wave_out_q,
-		out_valid	=> out_valid,
-		debug_out	=> debug_out
+		out_valid	=> out_valid
 	);
 
  	tb_clk : PROCESS
@@ -265,16 +262,14 @@ BEGIN
 	file RESULT_Q:      text open write_mode is "q_ud.txt"; 
 	file RESULT_ID:      text open write_mode is "i_d.txt"; 
 	file RESULT_QD:      text open write_mode is "q_d.txt"; 
-	file RESULT_LFSR:   text open write_mode is "lfsr.txt"; 
 	variable L:         line;
 
 	BEGIN
 		if rising_edge(clk) and fileout_enable = '1' and out_valid = '1' then
-			fprint(RESULT_I, L,"%s\n", REAL'image(debug_out.i_ud));
-			fprint(RESULT_Q, L,"%s\n", REAL'image(debug_out.q_ud));
-			fprint(RESULT_ID, L,"%s\n", REAL'image(debug_out.i_d));
-			fprint(RESULT_QD, L,"%s\n", REAL'image(debug_out.q_d));
-			fprint(RESULT_LFSR, L,"%s\n", INTEGER'image(to_integer(debug_out.lfsr)));
+			fprint(RESULT_I, L,"%s\n", REAL'image(to_real(wave_out_i)));
+			fprint(RESULT_Q, L,"%s\n", REAL'image(to_real(wave_out_q)));
+			fprint(RESULT_ID, L,"%s\n", REAL'image(to_real(wave_out_i)));
+			fprint(RESULT_QD, L,"%s\n", REAL'image(to_real(wave_out_q)));
 		end if;
 
 	END PROCESS;