- added interrupt enable
Committed on the Free edition of March Hare Software CVSNT Server. Upgrade to CVS Suite for more features and support: http://march-hare.com/cvsnt/ git-svn-id: http://moon:8086/svn/vhdl/trunk@456 cc03376c-175c-47c8-b038-4cd826a8556b
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@@ -68,8 +68,9 @@ ARCHITECTURE behavior OF uart_wb IS
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signal rx_full : std_logic;
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signal rx_full : std_logic;
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signal rx_half_full : std_logic;
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signal rx_half_full : std_logic;
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signal uart_status_port : unsigned(7 downto 0);
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signal uart_status_port : unsigned(7 downto 0);
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signal reg_uart_ctrl : unsigned(7 downto 0);
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signal reg_uart_baud : unsigned(7 downto 0);
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signal reg_uart_baud : unsigned(7 downto 0);
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signal rx_int_en : std_logic;
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signal tx_int_en : std_logic;
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begin
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begin
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@@ -83,7 +84,8 @@ registers_write:
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reg_we_uart_tx <= '0';
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reg_we_uart_tx <= '0';
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if RST_I = '1' then
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if RST_I = '1' then
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reg_uart_baud <= to_unsigned(53, 8);
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reg_uart_baud <= to_unsigned(53, 8);
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reg_uart_ctrl <= to_unsigned(0, 8);
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rx_int_en <= '0';
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tx_int_en <= '0';
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elsif (STB_I and CYC_I and WE_I) = '1' then
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elsif (STB_I and CYC_I and WE_I) = '1' then
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case ADDR_I(5 downto 2) is
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case ADDR_I(5 downto 2) is
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@@ -92,7 +94,8 @@ registers_write:
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reg_uart_tx <= DAT_I(7 downto 0);
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reg_uart_tx <= DAT_I(7 downto 0);
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when "0001" =>
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when "0001" =>
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reg_uart_ctrl <= DAT_I(7 downto 0);
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rx_int_en <= DAT_I(6);
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tx_int_en <= DAT_I(5);
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when "0010" =>
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when "0010" =>
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reg_uart_baud <= DAT_I(7 downto 0);
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reg_uart_baud <= DAT_I(7 downto 0);
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@@ -173,8 +176,8 @@ inst_uart_rx: uart_rx
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clk => CLK_I
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clk => CLK_I
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);
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);
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uart_status_port <= (7 downto 5 => '0') & rx_data_present & rx_full & rx_half_full & tx_full & tx_half_full;
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uart_status_port <= '0' & rx_int_en & tx_int_en & rx_data_present & rx_full & rx_half_full & tx_full & tx_half_full;
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INT_RX_O <= rx_data_present;
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INT_RX_O <= rx_data_present and rx_int_en;
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INT_TX_O <= not tx_full;
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INT_TX_O <= not tx_full and tx_int_en;
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end behavior;
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end behavior;
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