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- added interrupt enable

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git-svn-id: http://moon:8086/svn/vhdl/trunk@456 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
jens
2009-04-19 17:56:47 +00:00
parent cd867dad7d
commit d97c9dd6ec
1 changed files with 9 additions and 6 deletions
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lib/uart/uart_wb.vhd
+9 -6
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@@ -68,8 +68,9 @@ ARCHITECTURE behavior OF uart_wb IS
signal rx_full : std_logic;
signal rx_half_full : std_logic;
signal uart_status_port : unsigned(7 downto 0);
signal reg_uart_ctrl : unsigned(7 downto 0);
signal reg_uart_baud : unsigned(7 downto 0);
signal rx_int_en : std_logic;
signal tx_int_en : std_logic;
begin
@@ -83,7 +84,8 @@ registers_write:
reg_we_uart_tx <= '0';
if RST_I = '1' then
reg_uart_baud <= to_unsigned(53, 8);
reg_uart_ctrl <= to_unsigned(0, 8);
rx_int_en <= '0';
tx_int_en <= '0';
elsif (STB_I and CYC_I and WE_I) = '1' then
case ADDR_I(5 downto 2) is
@@ -92,7 +94,8 @@ registers_write:
reg_uart_tx <= DAT_I(7 downto 0);
when "0001" =>
reg_uart_ctrl <= DAT_I(7 downto 0);
rx_int_en <= DAT_I(6);
tx_int_en <= DAT_I(5);
when "0010" =>
reg_uart_baud <= DAT_I(7 downto 0);
@@ -173,8 +176,8 @@ inst_uart_rx: uart_rx
clk => CLK_I
);
uart_status_port <= (7 downto 5 => '0') & rx_data_present & rx_full & rx_half_full & tx_full & tx_half_full;
INT_RX_O <= rx_data_present;
INT_TX_O <= not tx_full;
uart_status_port <= '0' & rx_int_en & tx_int_en & rx_data_present & rx_full & rx_half_full & tx_full & tx_half_full;
INT_RX_O <= rx_data_present and rx_int_en;
INT_TX_O <= not tx_full and tx_int_en;
end behavior;