diff --git a/lib/CPUs/MIPS/dist/files.dist b/lib/CPUs/MIPS/dist/files.dist
index 8bcf8b9..1c755f9 100644
--- a/lib/CPUs/MIPS/dist/files.dist
+++ b/lib/CPUs/MIPS/dist/files.dist
@@ -1,11 +1,8 @@
 ../../../misc/dpram_2w2r.vhd
 ../../../misc/dpram_1w1r.vhd
 ../../../FIFO/src/fifo_ctrl_pkg.vhd
-../../../FIFO/src/gray_counter.vhd
 ../../../FIFO/src/fifo_sync_ctrl.vhd
 ../../../FIFO/src/fifo_sync.vhd
-../../../FIFO/src/fifo_async_ctrl.vhd
-../../../FIFO/src/fifo_async.vhd
 
 ../../../uart/bbfifo_16x8.vhd
 ../../../uart/kcuart_rx.vhd
diff --git a/lib/CPUs/MIPS/dist/mdist b/lib/CPUs/MIPS/dist/mdist
index 836a7cb..0a1b380 100644
--- a/lib/CPUs/MIPS/dist/mdist
+++ b/lib/CPUs/MIPS/dist/mdist
@@ -8,10 +8,8 @@ DIST_DIR="./release/mips.r12"
 mkdir -p $DIST_DIR/src
 mkdir -p $DIST_DIR/sim
 mkdir -p $DIST_DIR/doc
-mkdir -p $DIST_DIR/bsp
 mkdir -p $DIST_DIR/tools
 
-cp -a ../bsp/* $DIST_DIR/bsp/
 cp -a ../doc/*.pdf $DIST_DIR/doc/
 cp -a ../doc/*.txt $DIST_DIR/doc/
 cp -a ../tools/* $DIST_DIR/tools/
diff --git a/lib/CPUs/MIPS/dist/tmpl/mips_sys.vhd b/lib/CPUs/MIPS/dist/tmpl/mips_sys.vhd
index 76e3bf5..b72df1d 100644
--- a/lib/CPUs/MIPS/dist/tmpl/mips_sys.vhd
+++ b/lib/CPUs/MIPS/dist/tmpl/mips_sys.vhd
@@ -200,7 +200,6 @@ inst_mips_top: entity work.mips_top
 		debug	=> debug,
 		nmi		=> nmi,
 		eb		=> eb,
-		cpu_clk	=> clk,
 		RST_I	=> rst,
 		CLK_I	=> clk,
 		ACK_I	=> ACK_I,
diff --git a/lib/CPUs/MIPS/dist/tmpl/notes.txt b/lib/CPUs/MIPS/dist/tmpl/notes.txt
index e8824c1..488c8e6 100644
--- a/lib/CPUs/MIPS/dist/tmpl/notes.txt
+++ b/lib/CPUs/MIPS/dist/tmpl/notes.txt
@@ -55,8 +55,6 @@ Changes in release 12
                            # which is already active in the previous cycle
   ...
 
-- mips_biu.vhd: added asynchronous BUS-FIFOs to support different clocks for CPU and BUS
-
 -----------------------------------------------------------------
 Changes in release 11
 -----------------------------------------------------------------
diff --git a/lib/CPUs/MIPS/doc/J-MIPS.txt b/lib/CPUs/MIPS/doc/J-MIPS.txt
index 43448cb..d272660 100644
--- a/lib/CPUs/MIPS/doc/J-MIPS.txt
+++ b/lib/CPUs/MIPS/doc/J-MIPS.txt
@@ -15,7 +15,6 @@ J-MIPS Features
 - J-Bus kompatible Bus Interface Unit (J-Bus ist im wesentlichen FIFO interface mit 'wichtigen' Signalnamen)
 - 1,2 DMIPS/MHz mit 16Kbyte I/D-Cache (Dhrystone 2.1, GCC 4.3)
 - Endianness umschaltbar zur Hard-reset Zeit
-- Unterschiedliche Frequenzen für CPU und BUS möglich
 
 -----------------------------------------------------------------
 Known Limitations