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- cleaned up

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git-svn-id: http://moon:8086/svn/vhdl/trunk@876 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
jens
2010-04-08 08:30:10 +00:00
parent 59da541fca
commit d7e039dc77
2 changed files with 182 additions and 104 deletions
Download Patch File Download Diff File Expand all files Collapse all files
lib/emac/emac_jb.vhd
+2 -1
View File
@@ -636,11 +636,12 @@ inst_piso : entity work.piso
(
rst => RST_I,
clk => mii_tx_clk,
dout_en => '1',
din_vld => tx_data_vld,
din_rdy => piso_din_rdy,
din_be => tx_fifo_dout(35 downto 32),
din => tx_fifo_dout(31 downto 0),
dout_en => mii_tx_en,
dout_vld => mii_tx_en,
dout => mii_tx
);
lib/emac/src/tb_emac_jb.vhd
+180 -103
View File
@@ -74,18 +74,38 @@ ARCHITECTURE behavior OF tb_emac_jb IS
signal piso_din_vld : std_logic := '0';
signal piso_din_rdy : std_logic;
signal piso_din_be : unsigned(7 downto 0) := (others => '0');
signal piso_din_be : unsigned(3 downto 0) := (others => '0');
signal piso_din : unsigned(31 downto 0) := (others => '-');
signal piso_dout_vld : std_logic;
signal piso_dout : unsigned(7 downto 0);
signal piso_dout_en : std_logic;
signal piso_dout : unsigned(3 downto 0);
signal piso2_din_vld : std_logic := '0';
signal piso2_din_rdy : std_logic;
signal piso2_din_be : unsigned(1 downto 0) := (others => '1');
signal piso2_din : unsigned(7 downto 0) := (others => '-');
signal piso2_dout_vld : std_logic;
signal piso2_dout : unsigned(3 downto 0);
signal piso2_dout_en : std_logic;
signal sipo_enable : std_logic := '0';
signal sipo_din_en : std_logic := '0';
signal sipo_din : unsigned(3 downto 0) := (others => '-');
signal sipo_rst : std_logic := '0';
signal sipo_din_vld : std_logic := '0';
signal sipo_din : unsigned(7 downto 0) := (others => '-');
signal sipo_dout_vld : std_logic;
signal sipo_dout_be : unsigned(7 downto 0);
signal sipo_dout_en : std_logic;
signal sipo_dout_be : unsigned(3 downto 0);
signal sipo_dout : unsigned(31 downto 0);
signal sipo2_enable : std_logic := '0';
signal sipo2_rst : std_logic := '0';
signal sipo2_din_vld : std_logic := '0';
signal sipo2_din : unsigned(3 downto 0) := (others => '-');
signal sipo2_dout_vld : std_logic;
signal sipo2_dout_en : std_logic;
signal sipo2_dout_be : unsigned(1 downto 0);
signal sipo2_dout : unsigned(7 downto 0);
type emac_action_t is (emac_idle, emac_alloc, emac_write, emac_read);
signal emac_action : emac_action_t;
@@ -149,7 +169,7 @@ inst_piso : entity work.piso
GENERIC MAP
(
data_width_in => 32,
data_width_out => 4,
data_width_out => 8,
msb_first => true
)
PORT MAP
@@ -160,15 +180,43 @@ inst_piso : entity work.piso
din_rdy => piso_din_rdy,
din_be => piso_din_be,
din => piso_din,
dout_vld => piso_dout_vld,
dout_en => piso_dout_en,
dout => piso_dout
);
piso_dout_en <= '0'; --piso2_din_rdy;
inst_piso2 : entity work.piso
GENERIC MAP
(
data_width_in => 8,
data_width_out => 4,
msb_first => true
)
PORT MAP
(
rst => RST,
clk => CLK,
din_vld => piso2_din_vld,
din_rdy => piso2_din_rdy,
din_be => piso2_din_be,
din => piso2_din,
dout_vld => piso2_dout_vld,
dout_en => piso2_dout_en,
dout => piso2_dout
);
piso2_din_vld <= piso_dout_vld;
piso2_dout_en <= '1';
piso2_din <= piso_dout;
inst_sipo : entity work.sipo
GENERIC MAP
(
data_width_in => 4,
data_width_in => 8,
data_width_out => 32,
msb_first => true
)
@@ -176,16 +224,44 @@ inst_sipo : entity work.sipo
(
rst => RST,
clk => CLK,
enable => sipo_enable,
din_en => sipo_din_en,
din_en => sipo_enable,
din_vld => sipo_din_vld,
din => sipo_din,
dout_be => sipo_dout_be,
dout_vld => sipo_dout_vld,
dout => sipo_dout
dout => sipo_dout,
dout_en => sipo_dout_en
);
sipo_din <= piso_dout;
sipo_din_en <= piso_dout_en;
sipo_din <= sipo2_dout;
sipo_din_vld <= sipo2_dout_vld;
sipo_enable <= sipo2_dout_en;
sipo_rst <= RST or not piso2_dout_vld;
inst_sipo2 : entity work.sipo
GENERIC MAP
(
data_width_in => 4,
data_width_out => 8,
msb_first => true
)
PORT MAP
(
rst => RST,
clk => CLK,
din_en => sipo2_enable,
din_vld => sipo2_din_vld,
din => sipo2_din,
dout_be => sipo2_dout_be,
dout_vld => sipo2_dout_vld,
dout => sipo2_dout,
dout_en => sipo2_dout_en
);
sipo2_din <= piso2_dout;
sipo2_din_vld <= piso2_dout_vld;
sipo2_enable <= sipo2_din_vld;
sipo_rst <= RST or not piso2_dout_vld;
CLK_GEN: process
begin
@@ -306,117 +382,118 @@ STIMULUS: process
RST <= '0';
wait for 60*CLK_PERIOD;
emac_alloc (1536);
emac_write (1536);
emac_alloc (1536);
emac_write (1536);
-- emac_alloc (1536);
-- emac_write (1536);
--
-- emac_alloc (1536);
-- emac_write (1536);
--
-- emac_alloc (1536);
-- emac_write (1536);
--
-- emac_alloc (1536);
-- emac_write (1536);
--
-- emac_alloc (1536);
-- emac_write (1536);
--
-- emac_alloc (1536);
-- emac_write (1536);
--
-- emac_alloc (1536);
-- emac_write (1536);
--
-- emac_alloc (64);
-- emac_write (64);
--
-- emac_alloc (512);
-- emac_write (512);
--
-- emac_alloc (1536);
-- emac_write (1536);
--
-- emac_alloc (65);
-- emac_write (65);
--
-- emac_alloc (66);
-- emac_write (66);
--
-- emac_alloc (67);
-- emac_write (67);
--
-- emac_alloc (512);
-- emac_write (64);
--
-- emac_alloc (128);
-- emac_write (128);
emac_alloc (1536);
emac_write (1536);
emac_alloc (1536);
emac_write (1536);
emac_alloc (1536);
emac_write (1536);
emac_alloc (1536);
emac_write (1536);
emac_alloc (1536);
emac_write (1536);
emac_alloc (64);
emac_write (64);
emac_alloc (512);
emac_write (512);
emac_alloc (1536);
emac_write (1536);
emac_alloc (65);
emac_write (65);
emac_alloc (66);
emac_write (66);
emac_alloc (67);
emac_write (67);
emac_alloc (512);
emac_write (512);
wait for 4000*CLK_PERIOD;
wait until rising_edge(CLK);
shift_din <= X"12345678";
shift_sa <= 0;
shift_din_vld <= '1';
wait until rising_edge(CLK);
shift_sa <= shift_sa + 1;
wait until rising_edge(CLK);
shift_sa <= shift_sa + 1;
wait until rising_edge(CLK);
shift_sa <= shift_sa + 1;
wait until rising_edge(CLK);
shift_sa <= shift_sa + 1;
wait until rising_edge(CLK);
shift_sa <= shift_sa + 1;
wait until rising_edge(CLK);
shift_sa <= shift_sa + 1;
wait until rising_edge(CLK);
shift_sa <= shift_sa + 1;
wait until rising_edge(CLK);
shift_sa <= 0;
wait until rising_edge(CLK);
shift_sa <= shift_sa - 1;
wait until rising_edge(CLK);
shift_sa <= shift_sa - 1;
wait until rising_edge(CLK);
shift_sa <= shift_sa - 1;
wait until rising_edge(CLK);
shift_sa <= shift_sa - 1;
wait until rising_edge(CLK);
shift_sa <= shift_sa - 1;
wait until rising_edge(CLK);
shift_sa <= shift_sa - 1;
wait until rising_edge(CLK);
shift_sa <= shift_sa - 1;
wait until rising_edge(CLK);
shift_din_vld <= '0';
-- wait for 4000*CLK_PERIOD;
--
-- wait until rising_edge(CLK);
-- shift_din <= X"12345678";
-- shift_sa <= 0;
-- shift_din_vld <= '1';
-- wait until rising_edge(CLK);
-- shift_sa <= shift_sa + 1;
-- wait until rising_edge(CLK);
-- shift_sa <= shift_sa + 1;
-- wait until rising_edge(CLK);
-- shift_sa <= shift_sa + 1;
-- wait until rising_edge(CLK);
-- shift_sa <= shift_sa + 1;
-- wait until rising_edge(CLK);
-- shift_sa <= shift_sa + 1;
-- wait until rising_edge(CLK);
-- shift_sa <= shift_sa + 1;
-- wait until rising_edge(CLK);
-- shift_sa <= shift_sa + 1;
-- wait until rising_edge(CLK);
--
-- shift_sa <= 0;
-- wait until rising_edge(CLK);
-- shift_sa <= shift_sa - 1;
-- wait until rising_edge(CLK);
-- shift_sa <= shift_sa - 1;
-- wait until rising_edge(CLK);
-- shift_sa <= shift_sa - 1;
-- wait until rising_edge(CLK);
-- shift_sa <= shift_sa - 1;
-- wait until rising_edge(CLK);
-- shift_sa <= shift_sa - 1;
-- wait until rising_edge(CLK);
-- shift_sa <= shift_sa - 1;
-- wait until rising_edge(CLK);
-- shift_sa <= shift_sa - 1;
--
-- wait until rising_edge(CLK);
-- shift_din_vld <= '0';
for i in 1 to 10 loop
wait until rising_edge(CLK);
sipo_enable <= '1';
piso_din_vld <= '1';
piso_din <= X"12345678";
piso_din_be <= "11111111";
piso_din_be <= "1111";
wait until rising_edge(CLK) and piso_din_rdy = '1';
piso_din <= piso_din + X"12345678";
piso_din_be <= "11100111";
piso_din_be <= "1111";
wait until rising_edge(CLK) and piso_din_rdy = '1';
piso_din <= piso_din + X"12345678";
piso_din_be <= "11111100";
piso_din_be <= "1111";
wait until rising_edge(CLK) and piso_din_rdy = '1';
piso_din <= piso_din + X"12345678";
piso_din_be <= "00111111";
piso_din_be <= "1100";
wait until rising_edge(CLK) and piso_din_rdy = '1';
piso_din <= (others => '-');
piso_din_vld <= '0';
wait until rising_edge(CLK) and sipo_dout_vld = '1';
wait until rising_edge(CLK);
wait until rising_edge(CLK) and sipo_dout_vld = '1';
sipo_enable <= '0';
wait until rising_edge(CLK) and piso_dout_vld = '0';
-- wait until rising_edge(CLK);
-- wait until rising_edge(CLK) and sipo_dout_vld = '1';
--
wait for 33*CLK_PERIOD;
end loop;