From d7d8e55e83ffdbf3c93d7c033db212ba4135b030 Mon Sep 17 00:00:00 2001 From: Jens Ahrensfeld Date: Thu, 25 Mar 2021 12:54:39 +0000 Subject: [PATCH] - fixed paths after refactoring git-svn-id: http://moon:8086/svn/vhdl/trunk@1535 cc03376c-175c-47c8-b038-4cd826a8556b --- .../ise101/mips_sys/project/mips_sys.prj | 30 +++++++++---------- 1 file changed, 15 insertions(+), 15 deletions(-) diff --git a/projects/mips_sys/ise101/mips_sys/project/mips_sys.prj b/projects/mips_sys/ise101/mips_sys/project/mips_sys.prj index da5b49c..c9e5d95 100644 --- a/projects/mips_sys/ise101/mips_sys/project/mips_sys.prj +++ b/projects/mips_sys/ise101/mips_sys/project/mips_sys.prj @@ -2,21 +2,21 @@ vhdl work "../../../../lib/CPUs/MIPS/src/core/mips_types.vhd" vhdl work "../../src/bootloader_flash.ROM.vhd" vhdl work "../../../../lib/misc/utils_pkg.vhd" vhdl work "../../../../lib/misc/singleshot.vhd" -vhdl work "../../../../lib/misc/rom_wb.vhd" +vhdl work "../../../../lib/JBUS/memory/src/rom_wb.vhd" vhdl work "../../../../lib/misc/lcd_port.vhd" -vhdl work "../../../../lib/misc/gpio_wb.vhd" -vhdl work "../../../../lib/misc/async_types.vhd" -vhdl work "../../../../lib/misc/async_port_wb.vhd" -vhdl work "../../../../lib/rams/dpram_1w1r2c_ro_xil.vhd" -vhdl work "../../../../lib/rams/dpram_1w1r2c_ra_xil.vhd" +vhdl work "../../../../lib/JBUS/gpio/src/gpio_wb.vhd" +vhdl work "../../../../lib/JBUS/async_port/src/async_types.vhd" +vhdl work "../../../../lib/JBUS/async_port/src/async_port_wb.vhd" +vhdl work "../../../../lib/rams/xilinx/src/dpram_1w1r2c_ro.vhd" +vhdl work "../../../../lib/rams/xilinx/src/dpram_1w1r2c_ra.vhd" vhdl work "../../../../lib/FIFO/src/fifo_ctrl_pkg.vhd" vhdl work "../../../../lib/FIFO/src/gray_counter.vhd" vhdl work "../../../../lib/FIFO/src/fifo_sync_ctrl.vhd" vhdl work "../../../../lib/FIFO/src/fifo_async_ctrl.vhd" vhdl work "../../../../lib/FIFO/src/fifo_sync.vhd" vhdl work "../../../../lib/FIFO/src/fifo_async.vhd" -vhdl work "../../src/sdram_config.vhd" vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_const.vhd" +vhdl work "../../src/sdram_config.vhd" vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_types.vhd" vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_5/src/ddr_clk_virtex4.vhd" vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl.vhd" @@ -25,14 +25,14 @@ vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_5/src/ddr_phy_virtex4.vhd" vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_top.vhd" vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_frontend_wb64.vhd" vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_5/src/ctrl_ddr_wb64.vhd" -vhdl work "../../../../lib/misc/bbfifo.vhd" -vhdl work "../../../../lib/uart/uart_types.vhd" -vhdl work "../../../../lib/uart/juart_tx.vhd" -vhdl work "../../../../lib/uart/juart_rx.vhd" -vhdl work "../../../../lib/uart/uart_tx.vhd" -vhdl work "../../../../lib/uart/uart_rx.vhd" -vhdl work "../../../../lib/uart/uart.vhd" -vhdl work "../../../../lib/uart/uart_wb.vhd" +vhdl work "../../../../lib/misc/bbfifo/src/bbfifo.vhd" +vhdl work "../../../../lib/uart/src/uart_types.vhd" +vhdl work "../../../../lib/uart/src/generic/juart/juart_tx.vhd" +vhdl work "../../../../lib/uart/src/generic/juart/juart_rx.vhd" +vhdl work "../../../../lib/uart/src/generic/uart_tx.vhd" +vhdl work "../../../../lib/uart/src/generic/uart_rx.vhd" +vhdl work "../../../../lib/uart/src/generic/uart.vhd" +vhdl work "../../../../lib/uart/src/uart_wb.vhd" vhdl work "../../../../lib/emac/src/sipo.vhd" vhdl work "../../../../lib/emac/src/piso.vhd" vhdl work "../../../../lib/emac/src/emac_types.vhd"