diff --git a/projects/mips_de0_nano/quartus/mips/JMips.qsf b/projects/mips_de0_nano/quartus/mips/JMips.qsf
index 17853af..cd17cd5 100644
--- a/projects/mips_de0_nano/quartus/mips/JMips.qsf
+++ b/projects/mips_de0_nano/quartus/mips/JMips.qsf
@@ -103,17 +103,17 @@ set_global_assignment -name EDA_FLATTEN_BUSES OFF -section_id eda_simulation
 set_global_assignment -name SYNCHRONIZER_IDENTIFICATION AUTO
 set_global_assignment -name EDA_NATIVELINK_SIMULATION_SETUP_SCRIPT simulation/modelsim/run_msim_gate_vhdl.do -section_id eda_simulation
 set_global_assignment -name EDA_SIMULATION_RUN_SCRIPT simulation/modelsim/run_msim_gate_vhdl.do -section_id eda_simulation
-set_global_assignment -name EDA_TEST_BENCH_FILE ../../../../../repos/lib/CPUs/MIPS/src/bootloader.ROM.vhd -section_id TestBench
-set_global_assignment -name EDA_TEST_BENCH_FILE ../../../../../repos/lib/misc/async_types.vhd -section_id TestBench
-set_global_assignment -name EDA_TEST_BENCH_FILE ../../../../../repos/lib/CPUs/MIPS/src/async_defs.vhd -section_id TestBench
-set_global_assignment -name EDA_TEST_BENCH_FILE ../../../../../repos/lib/misc/async_port_wb.vhd -section_id TestBench
-set_global_assignment -name EDA_TEST_BENCH_FILE ../../../../../repos/lib/misc/gpio_wb.vhd -section_id TestBench
-set_global_assignment -name EDA_TEST_BENCH_FILE ../../../../../repos/lib/misc/rom_wb.vhd -section_id TestBench
-set_global_assignment -name EDA_TEST_BENCH_FILE ../../../../../repos/lib/uart/uart_wb.vhd -section_id TestBench
-set_global_assignment -name EDA_TEST_BENCH_FILE ../../../../../repos/lib/uart/uart_rx_sim.vhd -section_id TestBench
-set_global_assignment -name EDA_TEST_BENCH_FILE ../../../../../repos/lib/uart/uart_tx_sim.vhd -section_id TestBench
-set_global_assignment -name EDA_TEST_BENCH_FILE ../../../../../repos/lib/CPUs/MIPS/src/core/mips_types.vhd -section_id TestBench
-set_global_assignment -name EDA_TEST_BENCH_FILE ../../../../../repos/lib/CPUs/MIPS/src/tb_mips_top.vhd -section_id TestBench
+set_global_assignment -name EDA_TEST_BENCH_FILE ../../../../lib/CPUs/MIPS/src/bootloader.ROM.vhd -section_id TestBench
+set_global_assignment -name EDA_TEST_BENCH_FILE ../../../../lib/misc/async_types.vhd -section_id TestBench
+set_global_assignment -name EDA_TEST_BENCH_FILE ../../../../lib/CPUs/MIPS/src/async_defs.vhd -section_id TestBench
+set_global_assignment -name EDA_TEST_BENCH_FILE ../../../../lib/misc/async_port_wb.vhd -section_id TestBench
+set_global_assignment -name EDA_TEST_BENCH_FILE ../../../../lib/misc/gpio_wb.vhd -section_id TestBench
+set_global_assignment -name EDA_TEST_BENCH_FILE ../../../../lib/misc/rom_wb.vhd -section_id TestBench
+set_global_assignment -name EDA_TEST_BENCH_FILE ../../../../lib/uart/uart_wb.vhd -section_id TestBench
+set_global_assignment -name EDA_TEST_BENCH_FILE ../../../../lib/uart/uart_rx_sim.vhd -section_id TestBench
+set_global_assignment -name EDA_TEST_BENCH_FILE ../../../../lib/uart/uart_tx_sim.vhd -section_id TestBench
+set_global_assignment -name EDA_TEST_BENCH_FILE ../../../../lib/CPUs/MIPS/src/core/mips_types.vhd -section_id TestBench
+set_global_assignment -name EDA_TEST_BENCH_FILE ../../../../lib/CPUs/MIPS/src/tb_mips_top.vhd -section_id TestBench
 set_global_assignment -name ALLOW_REGISTER_MERGING ON
 set_global_assignment -name ALLOW_REGISTER_DUPLICATION ON
 set_global_assignment -name ALLOW_REGISTER_RETIMING ON
@@ -257,58 +257,58 @@ set_location_assignment PIN_A3 -to uart_rx[1]
 set_location_assignment PIN_C3 -to uart_tx[0]
 set_location_assignment PIN_B4 -to uart_tx[1]
 set_global_assignment -name VHDL_FILE "Z:/work/repos/mips/src/bootloader/build/denano/eb/bootloader.elf.ROM.vhd"
-set_global_assignment -name VHDL_FILE ../../../../../repos/lib/spi/src/spi_flash_wb.vhd
-set_global_assignment -name VHDL_FILE ../../../../../repos/lib/spi/src/spi_types.vhd
-set_global_assignment -name VHDL_FILE ../../../../../repos/lib/spi/src/spi_master.vhd
+set_global_assignment -name VHDL_FILE ../../../../lib/spi/src/spi_flash_wb.vhd
+set_global_assignment -name VHDL_FILE ../../../../lib/spi/src/spi_types.vhd
+set_global_assignment -name VHDL_FILE ../../../../lib/spi/src/spi_master.vhd
 set_global_assignment -name SDC_FILE JMips.sdc
-set_global_assignment -name VHDL_FILE ../../../../../repos/lib/emac/src/sipo.vhd
-set_global_assignment -name VHDL_FILE ../../../../../repos/lib/emac/src/piso.vhd
-set_global_assignment -name VHDL_FILE ../../../../../repos/lib/SDRAM/ddr_sdr_v1_5/src/sdram_config_mt48lc16m16.vhd
-set_global_assignment -name VHDL_FILE ../../../../../repos/lib/SDRAM/ddr_sdr_v1_5/src/sdram_types.vhd
-set_global_assignment -name VHDL_FILE ../../../../../repos/lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_top.vhd
-set_global_assignment -name VHDL_FILE ../../../../../repos/lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_frontend_wb16.vhd
-set_global_assignment -name VHDL_FILE ../../../../../repos/lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl.vhd
-set_global_assignment -name VHDL_FILE ../../../../../repos/lib/SDRAM/ddr_sdr_v1_5/src/sdram_const.vhd
-set_global_assignment -name VHDL_FILE ../../../../../repos/lib/SDRAM/ddr_sdr_v1_5/src/sdram_cmd.vhd
-set_global_assignment -name VHDL_FILE ../../../../../repos/lib/SDRAM/ddr_sdr_v1_5/src/sdr_phy_de0nano.vhd
-set_global_assignment -name VHDL_FILE ../../../../../repos/lib/SDRAM/ddr_sdr_v1_5/src/sdr_clk_cycloneive.vhd
-set_global_assignment -name VHDL_FILE ../../../../../repos/lib/SDRAM/ddr_sdr_v1_5/src/ctrl_sdr_wb32.vhd
-set_global_assignment -name VHDL_FILE ../../../../../repos/lib/uart/uart_types.vhd
+set_global_assignment -name VHDL_FILE ../../../../lib/emac/src/sipo.vhd
+set_global_assignment -name VHDL_FILE ../../../../lib/emac/src/piso.vhd
+set_global_assignment -name VHDL_FILE ../../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_config_mt48lc16m16.vhd
+set_global_assignment -name VHDL_FILE ../../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_types.vhd
+set_global_assignment -name VHDL_FILE ../../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_top.vhd
+set_global_assignment -name VHDL_FILE ../../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_frontend_wb16.vhd
+set_global_assignment -name VHDL_FILE ../../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl.vhd
+set_global_assignment -name VHDL_FILE ../../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_const.vhd
+set_global_assignment -name VHDL_FILE ../../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_cmd.vhd
+set_global_assignment -name VHDL_FILE ../../../../lib/SDRAM/ddr_sdr_v1_5/src/sdr_phy_de0nano.vhd
+set_global_assignment -name VHDL_FILE ../../../../lib/SDRAM/ddr_sdr_v1_5/src/sdr_clk_cycloneive.vhd
+set_global_assignment -name VHDL_FILE ../../../../lib/SDRAM/ddr_sdr_v1_5/src/ctrl_sdr_wb32.vhd
+set_global_assignment -name VHDL_FILE ../../../../lib/uart/uart_types.vhd
 set_global_assignment -name VHDL_FILE ../../../../lib/misc/bbfifo.vhd
 set_global_assignment -name VHDL_FILE ../../../../lib/uart/uart_tx.vhd
 set_global_assignment -name VHDL_FILE ../../../../lib/uart/uart_rx.vhd
 set_global_assignment -name VHDL_FILE ../../../../lib/uart/uart.vhd
 set_global_assignment -name VHDL_FILE ../../../../lib/uart/juart_tx.vhd
 set_global_assignment -name VHDL_FILE ../../../../lib/uart/juart_rx.vhd
-set_global_assignment -name VHDL_FILE ../../../../../repos/lib/uart/uart_wb.vhd
-set_global_assignment -name VHDL_FILE ../../../../../repos/lib/rams/dpram_1w1r1c_ra_alt.vhd
-set_global_assignment -name VHDL_FILE ../../../../../repos/lib/misc/gpio_wb.vhd
-set_global_assignment -name VHDL_FILE ../../../../../repos/lib/misc/utils_pkg.vhd
-set_global_assignment -name VHDL_FILE ../../../../../repos/lib/misc/rom_wb.vhd
-set_global_assignment -name VHDL_FILE ../../../../../repos/lib/misc/ram_wb.vhd
-set_global_assignment -name VHDL_FILE ../../../../../repos/lib/rams/dpram_1w1r2c_ra_alt.vhd
-set_global_assignment -name VHDL_FILE ../../../../../repos/lib/rams/dpram_2w2r2c_ra_alt.vhd
-set_global_assignment -name VHDL_FILE ../../../../../repos/lib/FIFO/src/fifo_sync_ctrl.vhd
-set_global_assignment -name VHDL_FILE ../../../../../repos/lib/FIFO/src/fifo_sync.vhd
-set_global_assignment -name VHDL_FILE ../../../../../repos/lib/FIFO/src/fifo_ctrl_pkg.vhd
-set_global_assignment -name VHDL_FILE ../../../../../repos/lib/FIFO/src/gray_counter.vhd
-set_global_assignment -name VHDL_FILE ../../../../../repos/lib/FIFO/src/fifo_async_ctrl.vhd
-set_global_assignment -name VHDL_FILE ../../../../../repos/lib/FIFO/src/fifo_async.vhd
-set_global_assignment -name VHDL_FILE ../../../../../repos/lib/CPUs/MIPS/src/core/mips_types.vhd
-set_global_assignment -name VHDL_FILE ../../../../../repos/lib/CPUs/MIPS/src/core/mips_top.vhd
-set_global_assignment -name VHDL_FILE ../../../../../repos/lib/CPUs/MIPS/src/core/mips_shifter.vhd
-set_global_assignment -name VHDL_FILE ../../../../../repos/lib/CPUs/MIPS/src/core/mips_reg.vhd
-set_global_assignment -name VHDL_FILE ../../../../../repos/lib/CPUs/MIPS/src/core/mips_pipeline.vhd
-set_global_assignment -name VHDL_FILE ../../../../../repos/lib/CPUs/MIPS/src/core/mips_muldiv.vhd
-set_global_assignment -name VHDL_FILE ../../../../../repos/lib/CPUs/MIPS/src/core/mips_instr.vhd
-set_global_assignment -name VHDL_FILE ../../../../../repos/lib/CPUs/MIPS/src/core/mips_icache.vhd
-set_global_assignment -name VHDL_FILE ../../../../../repos/lib/CPUs/MIPS/src/core/mips_dcache.vhd
-set_global_assignment -name VHDL_FILE ../../../../../repos/lib/CPUs/MIPS/src/core/mips_cop.vhd
-set_global_assignment -name VHDL_FILE ../../../../../repos/lib/CPUs/MIPS/src/core/mips_biu.vhd
-set_global_assignment -name VHDL_FILE ../../../../../repos/lib/CPUs/MIPS/src/core/mips_bcu.vhd
-set_global_assignment -name VHDL_FILE ../../../../../repos/lib/CPUs/MIPS/src/core/mips_alu.vhd
+set_global_assignment -name VHDL_FILE ../../../../lib/uart/uart_wb.vhd
+set_global_assignment -name VHDL_FILE ../../../../lib/rams/dpram_1w1r1c_ra_alt.vhd
+set_global_assignment -name VHDL_FILE ../../../../lib/misc/gpio_wb.vhd
+set_global_assignment -name VHDL_FILE ../../../../lib/misc/utils_pkg.vhd
+set_global_assignment -name VHDL_FILE ../../../../lib/misc/rom_wb.vhd
+set_global_assignment -name VHDL_FILE ../../../../lib/misc/ram_wb.vhd
+set_global_assignment -name VHDL_FILE ../../../../lib/rams/dpram_1w1r2c_ra_alt.vhd
+set_global_assignment -name VHDL_FILE ../../../../lib/rams/dpram_2w2r2c_ra_alt.vhd
+set_global_assignment -name VHDL_FILE ../../../../lib/FIFO/src/fifo_sync_ctrl.vhd
+set_global_assignment -name VHDL_FILE ../../../../lib/FIFO/src/fifo_sync.vhd
+set_global_assignment -name VHDL_FILE ../../../../lib/FIFO/src/fifo_ctrl_pkg.vhd
+set_global_assignment -name VHDL_FILE ../../../../lib/FIFO/src/gray_counter.vhd
+set_global_assignment -name VHDL_FILE ../../../../lib/FIFO/src/fifo_async_ctrl.vhd
+set_global_assignment -name VHDL_FILE ../../../../lib/FIFO/src/fifo_async.vhd
+set_global_assignment -name VHDL_FILE ../../../../lib/CPUs/MIPS/src/core/mips_types.vhd
+set_global_assignment -name VHDL_FILE ../../../../lib/CPUs/MIPS/src/core/mips_top.vhd
+set_global_assignment -name VHDL_FILE ../../../../lib/CPUs/MIPS/src/core/mips_shifter.vhd
+set_global_assignment -name VHDL_FILE ../../../../lib/CPUs/MIPS/src/core/mips_reg.vhd
+set_global_assignment -name VHDL_FILE ../../../../lib/CPUs/MIPS/src/core/mips_pipeline.vhd
+set_global_assignment -name VHDL_FILE ../../../../lib/CPUs/MIPS/src/core/mips_muldiv.vhd
+set_global_assignment -name VHDL_FILE ../../../../lib/CPUs/MIPS/src/core/mips_instr.vhd
+set_global_assignment -name VHDL_FILE ../../../../lib/CPUs/MIPS/src/core/mips_icache.vhd
+set_global_assignment -name VHDL_FILE ../../../../lib/CPUs/MIPS/src/core/mips_dcache.vhd
+set_global_assignment -name VHDL_FILE ../../../../lib/CPUs/MIPS/src/core/mips_cop.vhd
+set_global_assignment -name VHDL_FILE ../../../../lib/CPUs/MIPS/src/core/mips_biu.vhd
+set_global_assignment -name VHDL_FILE ../../../../lib/CPUs/MIPS/src/core/mips_bcu.vhd
+set_global_assignment -name VHDL_FILE ../../../../lib/CPUs/MIPS/src/core/mips_alu.vhd
 set_global_assignment -name VHDL_FILE mips_sys.vhd
-set_global_assignment -name VHDL_FILE ../../../../../repos/lib/misc/jtag_reg_alt.vhd
+set_global_assignment -name VHDL_FILE ../../../../lib/misc/jtag_reg_alt.vhd
 set_location_assignment PIN_M1 -to dip_sw[0]
 set_location_assignment PIN_T8 -to dip_sw[1]
 set_location_assignment PIN_B9 -to dip_sw[2]
@@ -317,4 +317,4 @@ set_location_assignment PIN_R8 -to clk_brd
 set_location_assignment PIN_J15 -to rst_brd_n
 set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to clk_brd
 set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to rst_brd_n
-set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file
+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top