From d3c322ca48ceb089b90c0a0d61313ec9acf884ca Mon Sep 17 00:00:00 2001 From: Jens Ahrensfeld Date: Wed, 15 Apr 2009 13:22:31 +0000 Subject: [PATCH] - bugfix: wrong 'pa_offset' when big-endian and half-word load/store Committed on the Free edition of March Hare Software CVSNT Server. Upgrade to CVS Suite for more features and support: http://march-hare.com/cvsnt/ git-svn-id: http://moon:8086/svn/vhdl/trunk@431 cc03376c-175c-47c8-b038-4cd826a8556b --- lib/CPUs/MIPS/src/core/mips_pipeline.vhd | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/lib/CPUs/MIPS/src/core/mips_pipeline.vhd b/lib/CPUs/MIPS/src/core/mips_pipeline.vhd index 1138de4..987dd9d 100644 --- a/lib/CPUs/MIPS/src/core/mips_pipeline.vhd +++ b/lib/CPUs/MIPS/src/core/mips_pipeline.vhd @@ -563,8 +563,12 @@ proc_stage_DMEM_ADDR: if rising_edge(clk_1) then if sdu.EX_stall = '0' then EX_stage.va <= vaddr; - if c0_ctrl_in.RE = '1' then - EX_stage.pa_off <= not vaddr(1 downto 0); + if c0_ctrl_in.EB = '1' then + if ID_stage.ctrl.word2_en = '0' then + EX_stage.pa_off <= not vaddr(1 downto 0); + else + EX_stage.pa_off <= not vaddr(1) & vaddr(0); + end if; else EX_stage.pa_off <= vaddr(1 downto 0); end if;