jens/vhdl
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

Refactored after moving of VHDL make

Browse Source
This commit is contained in:
jens
2022-09-07 13:09:41 +02:00
parent cbc093e6e7
commit d3beeb0538
63 changed files with 94 additions and 94 deletions
Download Patch File Download Diff File Expand all files Collapse all files
make/defs.mk → Common/make/defs.mk
View File
make/ghdl.mk → Common/make/ghdl.mk
View File
make/ise.mk → Common/make/ise.mk
View File
make/package_new.inc → Common/make/package_new.inc
View File
make/tb_new.make → Common/make/tb_new.make
View File
lib/CPUs/JCpu/Makefile
+1 -1
View File
@@ -1,4 +1,4 @@
include $(VHDL_HOME)/make/defs.mk include $(VHDL_MAKE_HOME)/defs.mk
TOOL_PATH := $(VHDL_HOME)/tools/jcpu TOOL_PATH := $(VHDL_HOME)/tools/jcpu
.PHONY: install uninstall .PHONY: install uninstall
lib/CPUs/JCpu/ghdl/cpu_itest.make
+2 -2
View File
@@ -1,5 +1,5 @@
# ----------------------------------------------------------- # -----------------------------------------------------------
include $(VHDL_HOME)/make/defs.mk include $(VHDL_MAKE_HOME)/defs.mk
# ----------------------------------------------------------- # -----------------------------------------------------------
include jcpu_core.inc include jcpu_core.inc
@@ -14,5 +14,5 @@ TARGET := cpu_itest
ENTITY := tb_cpu ENTITY := tb_cpu
WAVE_FORMAT := ghw WAVE_FORMAT := ghw
include $(VHDL_HOME)/make/ghdl.mk include $(VHDL_MAKE_HOME)/ghdl.mk
lib/CPUs/JCpu/ghdl/jcpu_core.inc
+1 -1
View File
@@ -1,5 +1,5 @@
# ----------------------------------------------------------- # -----------------------------------------------------------
include $(VHDL_HOME)/make/defs.mk include $(VHDL_MAKE_HOME)/defs.mk
# ----------------------------------------------------------- # -----------------------------------------------------------
PKG_NAME := JCPU_CORE PKG_NAME := JCPU_CORE
lib/CPUs/JCpu/ghdl/mul8x8.make
+2 -2
View File
@@ -1,5 +1,5 @@
# ----------------------------------------------------------- # -----------------------------------------------------------
include $(VHDL_HOME)/make/defs.mk include $(VHDL_MAKE_HOME)/defs.mk
# ----------------------------------------------------------- # -----------------------------------------------------------
include jcpu_core.inc include jcpu_core.inc
@@ -13,5 +13,5 @@ TARGET := mul8x8
ENTITY := tb_cpu_embedded ENTITY := tb_cpu_embedded
WAVE_FORMAT := ghw WAVE_FORMAT := ghw
include $(VHDL_HOME)/make/ghdl.mk include $(VHDL_MAKE_HOME)/ghdl.mk
lib/CPUs/JCpu/ghdl/reti_issue.make
+2 -2
View File
@@ -1,5 +1,5 @@
# ----------------------------------------------------------- # -----------------------------------------------------------
include $(VHDL_HOME)/make/defs.mk include $(VHDL_MAKE_HOME)/defs.mk
# ----------------------------------------------------------- # -----------------------------------------------------------
include jcpu_core.inc include jcpu_core.inc
@@ -14,5 +14,5 @@ TARGET := reti_issue
ENTITY := tb_cpu ENTITY := tb_cpu
WAVE_FORMAT := ghw WAVE_FORMAT := ghw
include $(VHDL_HOME)/make/ghdl.mk include $(VHDL_MAKE_HOME)/ghdl.mk
lib/CPUs/JCpu/ghdl/tb_cpu_embedded.make
+2 -2
View File
@@ -1,5 +1,5 @@
# ----------------------------------------------------------- # -----------------------------------------------------------
include $(VHDL_HOME)/make/defs.mk include $(VHDL_MAKE_HOME)/defs.mk
# ----------------------------------------------------------- # -----------------------------------------------------------
include jcpu_core.inc include jcpu_core.inc
@@ -12,5 +12,5 @@ SRCS += ../src/tb_cpu_embedded.vhd
TARGET := tb_cpu_embedded TARGET := tb_cpu_embedded
ENTITY := tb_cpu_embedded ENTITY := tb_cpu_embedded
include $(VHDL_HOME)/make/ghdl.mk include $(VHDL_MAKE_HOME)/ghdl.mk
lib/CPUs/JCpu/ghdl/tb_cpu_embedded_with_uart.make
+2 -2
View File
@@ -1,5 +1,5 @@
# ----------------------------------------------------------- # -----------------------------------------------------------
include $(VHDL_HOME)/make/defs.mk include $(VHDL_MAKE_HOME)/defs.mk
# ----------------------------------------------------------- # -----------------------------------------------------------
include $(VHDL_HOME)/lib/uart/ghdl/uart_sim.inc include $(VHDL_HOME)/lib/uart/ghdl/uart_sim.inc
include jcpu_core.inc include jcpu_core.inc
@@ -16,5 +16,5 @@ TARGET := tb_cpu_embedded_with_uart
ENTITY := tb_cpu_embedded_with_uart ENTITY := tb_cpu_embedded_with_uart
RUN_TIME := 100us RUN_TIME := 100us
include $(VHDL_HOME)/make/ghdl.mk include $(VHDL_MAKE_HOME)/ghdl.mk
lib/CPUs/MIPS/ghdl/mips_core.inc
+1 -1
View File
@@ -1,5 +1,5 @@
# ----------------------------------------------------------- # -----------------------------------------------------------
include $(VHDL_HOME)/make/defs.mk include $(VHDL_MAKE_HOME)/defs.mk
include $(LIB_PATH)/FIFO/ghdl/fifo_sync.inc include $(LIB_PATH)/FIFO/ghdl/fifo_sync.inc
include $(LIB_PATH)/FIFO/ghdl/fifo_async.inc include $(LIB_PATH)/FIFO/ghdl/fifo_async.inc
lib/CPUs/MIPS/ghdl/tb_mips_top.make
+2 -2
View File
@@ -1,5 +1,5 @@
# ----------------------------------------------------------- # -----------------------------------------------------------
include $(VHDL_HOME)/make/defs.mk include $(VHDL_MAKE_HOME)/defs.mk
# ----------------------------------------------------------- # -----------------------------------------------------------
include mips_core.inc include mips_core.inc
@@ -34,5 +34,5 @@ TARGET := tb_mips_top
ENTITY := tb_mips_top ENTITY := tb_mips_top
RUN_TIME ?= 1500us RUN_TIME ?= 1500us
include $(VHDL_HOME)/make/ghdl.mk include $(VHDL_MAKE_HOME)/ghdl.mk
lib/CPUs/MIPS/syn/ise101/Makefile
+1 -1
View File
@@ -4,5 +4,5 @@ PRJ := mips_top
PREQ := $(PRJDIR)/$(PRJ).prj $(PRJDIR)/$(PRJ).xst $(PRJDIR)/$(PRJ).lso PREQ := $(PRJDIR)/$(PRJ).prj $(PRJDIR)/$(PRJ).xst $(PRJDIR)/$(PRJ).lso
DEVICE := "xc4vsx35-ff668-10" DEVICE := "xc4vsx35-ff668-10"
include $(VHDL_HOME)/make/ise.mk include $(VHDL_MAKE_HOME)/ise.mk
lib/FIFO/ghdl/fifo_async.inc
+1 -1
View File
@@ -1,5 +1,5 @@
# ----------------------------------------------------------- # -----------------------------------------------------------
include $(VHDL_HOME)/make/defs.mk include $(VHDL_MAKE_HOME)/defs.mk
# ----------------------------------------------------------- # -----------------------------------------------------------
PKG_NAME := FIFO_ASYNC PKG_NAME := FIFO_ASYNC
lib/FIFO/ghdl/fifo_sync.inc
+1 -1
View File
@@ -1,5 +1,5 @@
# ----------------------------------------------------------- # -----------------------------------------------------------
include $(VHDL_HOME)/make/defs.mk include $(VHDL_MAKE_HOME)/defs.mk
# ----------------------------------------------------------- # -----------------------------------------------------------
PKG_NAME := FIFO_SYNC PKG_NAME := FIFO_SYNC
lib/FIFO/ghdl/tb_fifo_async.make
+2 -2
View File
@@ -1,4 +1,4 @@
include $(VHDL_HOME)/make/defs.mk include $(VHDL_MAKE_HOME)/defs.mk
include fifo_async.inc include fifo_async.inc
ROOT_PATH := ../../.. ROOT_PATH := ../../..
@@ -12,5 +12,5 @@ TARGET := tb_fifo_async
ENTITY := tb_fifo_async ENTITY := tb_fifo_async
RUN_TIME := 5us RUN_TIME := 5us
include $(VHDL_HOME)/make/ghdl.mk include $(VHDL_MAKE_HOME)/ghdl.mk
lib/FIFO/ghdl/tb_fifo_sync.make
+2 -2
View File
@@ -1,4 +1,4 @@
include $(VHDL_HOME)/make/defs.mk include $(VHDL_MAKE_HOME)/defs.mk
include fifo_sync.inc include fifo_sync.inc
ROOT_PATH := ../../.. ROOT_PATH := ../../..
@@ -12,5 +12,5 @@ TARGET := tb_fifo_sync
ENTITY := tb_fifo_sync ENTITY := tb_fifo_sync
RUN_TIME := 5us RUN_TIME := 5us
include $(VHDL_HOME)/make/ghdl.mk include $(VHDL_MAKE_HOME)/ghdl.mk
lib/FIFO/ghdl/tb_gray_counter.make
+2 -2
View File
@@ -1,4 +1,4 @@
include $(VHDL_HOME)/make/defs.mk include $(VHDL_MAKE_HOME)/defs.mk
SRCS += $(LIB_PATH)/FIFO/src/fifo_ctrl_pkg.vhd SRCS += $(LIB_PATH)/FIFO/src/fifo_ctrl_pkg.vhd
SRCS += $(LIB_PATH)/FIFO/src/gray_counter.vhd SRCS += $(LIB_PATH)/FIFO/src/gray_counter.vhd
@@ -9,5 +9,5 @@ TARGET := tb_gray_counter
ENTITY := tb_gray_counter ENTITY := tb_gray_counter
RUN_TIME := 1us RUN_TIME := 1us
include $(VHDL_HOME)/make/ghdl.mk include $(VHDL_MAKE_HOME)/ghdl.mk
lib/FIFO/ghdl/tb_reg_stage.make
+2 -2
View File
@@ -1,4 +1,4 @@
include $(VHDL_HOME)/make/defs.mk include $(VHDL_MAKE_HOME)/defs.mk
SRCS += $(LIB_PATH)/FIFO/src/reg_stage.vhd SRCS += $(LIB_PATH)/FIFO/src/reg_stage.vhd
SRCS += $(LIB_PATH)/FIFO/src/tb_reg_stage.vhd SRCS += $(LIB_PATH)/FIFO/src/tb_reg_stage.vhd
@@ -8,5 +8,5 @@ TARGET := tb_reg_stage
ENTITY := tb_reg_stage ENTITY := tb_reg_stage
RUN_TIME := 1us RUN_TIME := 1us
include $(VHDL_HOME)/make/ghdl.mk include $(VHDL_MAKE_HOME)/ghdl.mk
lib/JBUS/busmaster/ghdl/tb_busmaster_async.make
+2 -2
View File
@@ -1,4 +1,4 @@
include $(VHDL_HOME)/make/defs.mk include $(VHDL_MAKE_HOME)/defs.mk
include $(LIB_PATH)/FIFO/ghdl/fifo_async.inc include $(LIB_PATH)/FIFO/ghdl/fifo_async.inc
MOD_PATH := $(LIB_PATH)/JBUS/busmaster MOD_PATH := $(LIB_PATH)/JBUS/busmaster
@@ -15,5 +15,5 @@ ENTITY := tb_busmaster_async
RUN_TIME := 80us RUN_TIME := 80us
WAVE_FORMAT := vcd WAVE_FORMAT := vcd
include $(VHDL_HOME)/make/ghdl.mk include $(VHDL_MAKE_HOME)/ghdl.mk
lib/JBUS/busmaster/ghdl/tb_busmaster_sync.make
+2 -2
View File
@@ -1,4 +1,4 @@
include $(VHDL_HOME)/make/defs.mk include $(VHDL_MAKE_HOME)/defs.mk
include $(LIB_PATH)/FIFO/ghdl/fifo_sync.inc include $(LIB_PATH)/FIFO/ghdl/fifo_sync.inc
MOD_PATH := $(LIB_PATH)/JBUS/busmaster MOD_PATH := $(LIB_PATH)/JBUS/busmaster
@@ -15,5 +15,5 @@ ENTITY := tb_busmaster_sync
RUN_TIME := 40us RUN_TIME := 40us
WAVE_FORMAT := vcd WAVE_FORMAT := vcd
include $(VHDL_HOME)/make/ghdl.mk include $(VHDL_MAKE_HOME)/ghdl.mk
lib/JBUS/dmac/ghdl/tb_dmac_sync.make
+2 -2
View File
@@ -1,4 +1,4 @@
include $(VHDL_HOME)/make/defs.mk include $(VHDL_MAKE_HOME)/defs.mk
include $(LIB_PATH)/FIFO/ghdl/fifo_sync.inc include $(LIB_PATH)/FIFO/ghdl/fifo_sync.inc
MOD_PATH := $(LIB_PATH)/JBUS MOD_PATH := $(LIB_PATH)/JBUS
@@ -16,5 +16,5 @@ ENTITY := tb_dmac
RUN_TIME := 6us RUN_TIME := 6us
WAVE_FORMAT := vcd WAVE_FORMAT := vcd
include $(VHDL_HOME)/make/ghdl.mk include $(VHDL_MAKE_HOME)/ghdl.mk
lib/JBUS/memory/ghdl/tb_ram_wb.make
+2 -2
View File
@@ -1,4 +1,4 @@
include $(VHDL_HOME)/make/defs.mk include $(VHDL_MAKE_HOME)/defs.mk
MOD_PATH := $(LIB_PATH)/JBUS/memory MOD_PATH := $(LIB_PATH)/JBUS/memory
@@ -13,4 +13,4 @@ ENTITY := tb_ram_wb
RUN_TIME := 1500ns RUN_TIME := 1500ns
WAVE_FORMAT := vcd WAVE_FORMAT := vcd
include $(VHDL_HOME)/make/ghdl.mk include $(VHDL_MAKE_HOME)/ghdl.mk
lib/JBUS/memory/ghdl/tb_rom_wb.make
+2 -2
View File
@@ -1,4 +1,4 @@
include $(VHDL_HOME)/make/defs.mk include $(VHDL_MAKE_HOME)/defs.mk
MOD_PATH := $(LIB_PATH)/JBUS/memory MOD_PATH := $(LIB_PATH)/JBUS/memory
@@ -12,5 +12,5 @@ ENTITY := tb_rom_wb
RUN_TIME := 1500ns RUN_TIME := 1500ns
WAVE_FORMAT := vcd WAVE_FORMAT := vcd
include $(VHDL_HOME)/make/ghdl.mk include $(VHDL_MAKE_HOME)/ghdl.mk
lib/SDRAM/ddr_sdr_v1_5/ghdl/tb_ctrl_ddr_wb32.make
+2 -2
View File
@@ -1,5 +1,5 @@
# ----------------------------------------------------------- # -----------------------------------------------------------
include $(VHDL_HOME)/make/defs.mk include $(VHDL_MAKE_HOME)/defs.mk
# ----------------------------------------------------------- # -----------------------------------------------------------
include $(LIB_PATH)/FIFO/ghdl/fifo_sync.inc include $(LIB_PATH)/FIFO/ghdl/fifo_sync.inc
include $(LIB_PATH)/FIFO/ghdl/fifo_async.inc include $(LIB_PATH)/FIFO/ghdl/fifo_async.inc
@@ -31,5 +31,5 @@ WAVE_FORMAT := vcd
GHDL_OPTS := -P$(VHDL_HOME)/Common/sim/build/ghdl/unisim -fsynopsys -fexplicit GHDL_OPTS := -P$(VHDL_HOME)/Common/sim/build/ghdl/unisim -fsynopsys -fexplicit
include $(VHDL_HOME)/make/ghdl.mk include $(VHDL_MAKE_HOME)/ghdl.mk
lib/SDRAM/ddr_sdr_v1_5/ghdl/tb_ctrl_ddr_wb64.make
+2 -2
View File
@@ -1,5 +1,5 @@
# ----------------------------------------------------------- # -----------------------------------------------------------
include $(VHDL_HOME)/make/defs.mk include $(VHDL_MAKE_HOME)/defs.mk
# ----------------------------------------------------------- # -----------------------------------------------------------
include $(LIB_PATH)/FIFO/ghdl/fifo_sync.inc include $(LIB_PATH)/FIFO/ghdl/fifo_sync.inc
include $(LIB_PATH)/FIFO/ghdl/fifo_async.inc include $(LIB_PATH)/FIFO/ghdl/fifo_async.inc
@@ -30,5 +30,5 @@ WAVE_FORMAT := vcd
GHDL_OPTS := -P$(VHDL_HOME)/Common/sim/build/ghdl/unisim -fsynopsys -fexplicit GHDL_OPTS := -P$(VHDL_HOME)/Common/sim/build/ghdl/unisim -fsynopsys -fexplicit
include $(VHDL_HOME)/make/ghdl.mk include $(VHDL_MAKE_HOME)/ghdl.mk
lib/VGA_ctrl/ghdl/tb_vga_frontend_jb32.make
+2 -2
View File
@@ -1,5 +1,5 @@
# ----------------------------------------------------------- # -----------------------------------------------------------
include $(VHDL_HOME)/make/defs.mk include $(VHDL_MAKE_HOME)/defs.mk
# ----------------------------------------------------------- # -----------------------------------------------------------
include vga_frontend_jb32.inc include vga_frontend_jb32.inc
@@ -13,6 +13,6 @@ TARGET := tb_vga_frontend_jb32
ENTITY := tb_vga_frontend_jb32 ENTITY := tb_vga_frontend_jb32
RUN_TIME := 20ms RUN_TIME := 20ms
include $(VHDL_HOME)/make/ghdl.mk include $(VHDL_MAKE_HOME)/ghdl.mk
# ----------------------------------------------------------- # -----------------------------------------------------------
lib/VGA_ctrl/ghdl/tb_vga_frontend_jb64.make
+2 -2
View File
@@ -1,5 +1,5 @@
# ----------------------------------------------------------- # -----------------------------------------------------------
include $(VHDL_HOME)/make/defs.mk include $(VHDL_MAKE_HOME)/defs.mk
# ----------------------------------------------------------- # -----------------------------------------------------------
include vga_frontend_jb64.inc include vga_frontend_jb64.inc
@@ -13,6 +13,6 @@ TARGET := tb_vga_frontend_jb64
ENTITY := tb_vga_frontend_jb64 ENTITY := tb_vga_frontend_jb64
RUN_TIME := 2ms RUN_TIME := 2ms
include $(VHDL_HOME)/make/ghdl.mk include $(VHDL_MAKE_HOME)/ghdl.mk
# ----------------------------------------------------------- # -----------------------------------------------------------
lib/VGA_ctrl/ghdl/vga_backend.inc
+1 -1
View File
@@ -1,5 +1,5 @@
# ----------------------------------------------------------- # -----------------------------------------------------------
include $(VHDL_HOME)/make/defs.mk include $(VHDL_MAKE_HOME)/defs.mk
# ----------------------------------------------------------- # -----------------------------------------------------------
PKG_NAME := VGA_BACKEND PKG_NAME := VGA_BACKEND
lib/VGA_ctrl/ghdl/vga_frontend_jb32.inc
+1 -1
View File
@@ -1,5 +1,5 @@
# ----------------------------------------------------------- # -----------------------------------------------------------
include $(VHDL_HOME)/make/defs.mk include $(VHDL_MAKE_HOME)/defs.mk
include vga_backend.inc include vga_backend.inc
include $(LIB_PATH)/FIFO/ghdl/fifo_async.inc include $(LIB_PATH)/FIFO/ghdl/fifo_async.inc
lib/VGA_ctrl/ghdl/vga_frontend_jb64.inc
+1 -1
View File
@@ -1,5 +1,5 @@
# ----------------------------------------------------------- # -----------------------------------------------------------
include $(VHDL_HOME)/make/defs.mk include $(VHDL_MAKE_HOME)/defs.mk
include $(LIB_PATH)/VGA_ctrl/ghdl/vga_backend.inc include $(LIB_PATH)/VGA_ctrl/ghdl/vga_backend.inc
include $(LIB_PATH)/FIFO/ghdl/fifo_sync.inc include $(LIB_PATH)/FIFO/ghdl/fifo_sync.inc
include $(LIB_PATH)/FIFO/ghdl/fifo_async.inc include $(LIB_PATH)/FIFO/ghdl/fifo_async.inc
lib/emac/ghdl/emac_jbus.inc
+1 -1
View File
@@ -1,5 +1,5 @@
# ----------------------------------------------------------- # -----------------------------------------------------------
include $(VHDL_HOME)/make/defs.mk include $(VHDL_MAKE_HOME)/defs.mk
# ----------------------------------------------------------- # -----------------------------------------------------------
include $(LIB_PATH)/emac/ghdl/emac_tx.inc include $(LIB_PATH)/emac/ghdl/emac_tx.inc
include $(LIB_PATH)/emac/ghdl/emac_rx.inc include $(LIB_PATH)/emac/ghdl/emac_rx.inc
lib/emac/ghdl/emac_rx.inc
+1 -1
View File
@@ -1,5 +1,5 @@
# ----------------------------------------------------------- # -----------------------------------------------------------
include $(VHDL_HOME)/make/defs.mk include $(VHDL_MAKE_HOME)/defs.mk
# ----------------------------------------------------------- # -----------------------------------------------------------
include $(LIB_PATH)/FIFO/ghdl/fifo_async.inc include $(LIB_PATH)/FIFO/ghdl/fifo_async.inc
lib/emac/ghdl/emac_tx.inc
+1 -1
View File
@@ -1,5 +1,5 @@
# ----------------------------------------------------------- # -----------------------------------------------------------
include $(VHDL_HOME)/make/defs.mk include $(VHDL_MAKE_HOME)/defs.mk
# ----------------------------------------------------------- # -----------------------------------------------------------
include $(LIB_PATH)/FIFO/ghdl/fifo_sync.inc include $(LIB_PATH)/FIFO/ghdl/fifo_sync.inc
include $(LIB_PATH)/FIFO/ghdl/fifo_async.inc include $(LIB_PATH)/FIFO/ghdl/fifo_async.inc
lib/emac/ghdl/tb_emac_top_jb.make
+2 -2
View File
@@ -1,4 +1,4 @@
include $(VHDL_HOME)/make/defs.mk include $(VHDL_MAKE_HOME)/defs.mk
include emac_jbus.inc include emac_jbus.inc
SRCS := $(EMAC_JBUS_SRCS) SRCS := $(EMAC_JBUS_SRCS)
@@ -10,5 +10,5 @@ TARGET := tb_emac_top_jb
ENTITY := tb_emac_top_jb ENTITY := tb_emac_top_jb
RUN_TIME := 2000us RUN_TIME := 2000us
include $(VHDL_HOME)/make/ghdl.mk include $(VHDL_MAKE_HOME)/ghdl.mk
lib/filter/ghdl/fir_iterative.inc
+1 -1
View File
@@ -1,5 +1,5 @@
# ----------------------------------------------------------- # -----------------------------------------------------------
include $(VHDL_HOME)/make/defs.mk include $(VHDL_MAKE_HOME)/defs.mk
# ----------------------------------------------------------- # -----------------------------------------------------------
PKG_NAME := FIR_ITERATIVE PKG_NAME := FIR_ITERATIVE
lib/filter/ghdl/fir_parallel.inc
+1 -1
View File
@@ -1,5 +1,5 @@
# ----------------------------------------------------------- # -----------------------------------------------------------
include $(VHDL_HOME)/make/defs.mk include $(VHDL_MAKE_HOME)/defs.mk
# ----------------------------------------------------------- # -----------------------------------------------------------
PKG_NAME := FIR_PARALLEL PKG_NAME := FIR_PARALLEL
lib/filter/ghdl/fir_semi_parallel.inc
+1 -1
View File
@@ -1,5 +1,5 @@
# ----------------------------------------------------------- # -----------------------------------------------------------
include $(VHDL_HOME)/make/defs.mk include $(VHDL_MAKE_HOME)/defs.mk
# ----------------------------------------------------------- # -----------------------------------------------------------
PKG_NAME := FIR_SEMI_PARALLEL PKG_NAME := FIR_SEMI_PARALLEL
lib/filter/ghdl/tb_fir_iterative.make
+2 -2
View File
@@ -1,4 +1,4 @@
include $(VHDL_HOME)/make/defs.mk include $(VHDL_MAKE_HOME)/defs.mk
include fir_iterative.inc include fir_iterative.inc
ROOT_PATH := ../../.. ROOT_PATH := ../../..
@@ -15,5 +15,5 @@ ENTITY := tb_fir_iterative
GHDL_OPTS := -P$(LIB_PATH)/fixed/ieee_proposed/build/fixed_pkg/ieee_proposed GHDL_OPTS := -P$(LIB_PATH)/fixed/ieee_proposed/build/fixed_pkg/ieee_proposed
RUN_TIME := 6us RUN_TIME := 6us
include $(VHDL_HOME)/make/ghdl.mk include $(VHDL_MAKE_HOME)/ghdl.mk
lib/filter/ghdl/tb_fir_parallel.make
+2 -2
View File
@@ -1,4 +1,4 @@
include $(VHDL_HOME)/make/defs.mk include $(VHDL_MAKE_HOME)/defs.mk
include fir_parallel.inc include fir_parallel.inc
ROOT_PATH := ../../.. ROOT_PATH := ../../..
@@ -15,5 +15,5 @@ ENTITY := tb_fir_parallel
GHDL_OPTS := -P$(LIB_PATH)/fixed/ieee_proposed/build/fixed_pkg/ieee_proposed GHDL_OPTS := -P$(LIB_PATH)/fixed/ieee_proposed/build/fixed_pkg/ieee_proposed
RUN_TIME := 200us RUN_TIME := 200us
include $(VHDL_HOME)/make/ghdl.mk include $(VHDL_MAKE_HOME)/ghdl.mk
lib/filter/ghdl/tb_fir_semi_parallel.make
+2 -2
View File
@@ -1,4 +1,4 @@
include $(VHDL_HOME)/make/defs.mk include $(VHDL_MAKE_HOME)/defs.mk
include fir_semi_parallel.inc include fir_semi_parallel.inc
ROOT_PATH := ../../.. ROOT_PATH := ../../..
@@ -15,5 +15,5 @@ ENTITY := tb_fir_semi_parallel
GHDL_OPTS := -P$(LIB_PATH)/fixed/ieee_proposed/build/fixed_pkg/ieee_proposed GHDL_OPTS := -P$(LIB_PATH)/fixed/ieee_proposed/build/fixed_pkg/ieee_proposed
RUN_TIME := 50us RUN_TIME := 50us
include $(VHDL_HOME)/make/ghdl.mk include $(VHDL_MAKE_HOME)/ghdl.mk
lib/filter/ghdl/tb_fir_stage.make
+2 -2
View File
@@ -1,4 +1,4 @@
include $(VHDL_HOME)/make/defs.mk include $(VHDL_MAKE_HOME)/defs.mk
SRCS += $(LIB_PATH)/PCK_FIO-2002.7/PCK_FIO_1993.vhd SRCS += $(LIB_PATH)/PCK_FIO-2002.7/PCK_FIO_1993.vhd
SRCS += $(LIB_PATH)/PCK_FIO-2002.7/PCK_FIO_1993_BODY.vhd SRCS += $(LIB_PATH)/PCK_FIO-2002.7/PCK_FIO_1993_BODY.vhd
@@ -15,5 +15,5 @@ ENTITY := tb_fir_stage
GHDL_OPTS := -P$(LIB_PATH)/fixed/ieee_proposed/build/fixed_pkg/ieee_proposed GHDL_OPTS := -P$(LIB_PATH)/fixed/ieee_proposed/build/fixed_pkg/ieee_proposed
RUN_TIME := 2us RUN_TIME := 2us
include $(VHDL_HOME)/make/ghdl.mk include $(VHDL_MAKE_HOME)/ghdl.mk
lib/filter/ghdl/tb_fir_stage_sys.make
+2 -2
View File
@@ -1,4 +1,4 @@
include $(VHDL_HOME)/make/defs.mk include $(VHDL_MAKE_HOME)/defs.mk
SRCS += $(LIB_PATH)/PCK_FIO-2002.7/PCK_FIO_1993.vhd SRCS += $(LIB_PATH)/PCK_FIO-2002.7/PCK_FIO_1993.vhd
SRCS += $(LIB_PATH)/PCK_FIO-2002.7/PCK_FIO_1993_BODY.vhd SRCS += $(LIB_PATH)/PCK_FIO-2002.7/PCK_FIO_1993_BODY.vhd
@@ -15,5 +15,5 @@ ENTITY := tb_fir_stage_sys
GHDL_OPTS := -P$(LIB_PATH)/fixed/ieee_proposed/build/fixed_pkg/ieee_proposed GHDL_OPTS := -P$(LIB_PATH)/fixed/ieee_proposed/build/fixed_pkg/ieee_proposed
RUN_TIME := 2us RUN_TIME := 2us
include $(VHDL_HOME)/make/ghdl.mk include $(VHDL_MAKE_HOME)/ghdl.mk
lib/ps2_port/ghdl/tb_ps2_core.make
+2 -2
View File
@@ -1,4 +1,4 @@
include $(VHDL_HOME)/make/defs.mk include $(VHDL_MAKE_HOME)/defs.mk
MOD_PATH := $(VHDL_HOME)/lib/ps2_port MOD_PATH := $(VHDL_HOME)/lib/ps2_port
@@ -11,5 +11,5 @@ ENTITY := tb_ps2_core
RUN_TIME := 10ms RUN_TIME := 10ms
WAVE_FORMAT := vcd WAVE_FORMAT := vcd
include $(VHDL_HOME)/make/ghdl.mk include $(VHDL_MAKE_HOME)/ghdl.mk
lib/radio/cordic/ghdl/cordic_iterative.inc
+1 -1
View File
@@ -1,5 +1,5 @@
# ----------------------------------------------------------- # -----------------------------------------------------------
include $(VHDL_HOME)/make/defs.mk include $(VHDL_MAKE_HOME)/defs.mk
# ----------------------------------------------------------- # -----------------------------------------------------------
PKG_NAME := CORDIC_ITERATIVE PKG_NAME := CORDIC_ITERATIVE
lib/radio/cordic/ghdl/cordic_pipe.inc
+1 -1
View File
@@ -1,5 +1,5 @@
# ----------------------------------------------------------- # -----------------------------------------------------------
include $(VHDL_HOME)/make/defs.mk include $(VHDL_MAKE_HOME)/defs.mk
# ----------------------------------------------------------- # -----------------------------------------------------------
PKG_NAME := CORDIC_PIPE PKG_NAME := CORDIC_PIPE
lib/radio/cordic/ghdl/tb_cordic_iterative_top.make
+2 -2
View File
@@ -1,5 +1,5 @@
# ------------------------------------------------- # -------------------------------------------------
include $(VHDL_HOME)/make/defs.mk include $(VHDL_MAKE_HOME)/defs.mk
include cordic_iterative.inc include cordic_iterative.inc
# ------------------------------------------------- # -------------------------------------------------
@@ -26,5 +26,5 @@ WAVE_FORMAT := vcd
GHDL_OPTS := -P$(LIB_PATH)/fixed/ieee_proposed/build/fixed_pkg/ieee_proposed GHDL_OPTS := -P$(LIB_PATH)/fixed/ieee_proposed/build/fixed_pkg/ieee_proposed
include $(VHDL_HOME)/make/ghdl.mk include $(VHDL_MAKE_HOME)/ghdl.mk
# ------------------------------------------------- # -------------------------------------------------
lib/radio/cordic/ghdl/tb_cordic_pipe_top.make
+2 -2
View File
@@ -1,5 +1,5 @@
# ------------------------------------------------- # -------------------------------------------------
include $(VHDL_HOME)/make/defs.mk include $(VHDL_MAKE_HOME)/defs.mk
include cordic_pipe.inc include cordic_pipe.inc
# ------------------------------------------------- # -------------------------------------------------
@@ -26,6 +26,6 @@ WAVE_FORMAT := vcd
GHDL_OPTS := -P$(LIB_PATH)/fixed/ieee_proposed/build/fixed_pkg/ieee_proposed GHDL_OPTS := -P$(LIB_PATH)/fixed/ieee_proposed/build/fixed_pkg/ieee_proposed
include $(VHDL_HOME)/make/ghdl.mk include $(VHDL_MAKE_HOME)/ghdl.mk
# ------------------------------------------------- # -------------------------------------------------
lib/radio/ddc/ghdl/tb_ddc.make
+2 -2
View File
@@ -1,4 +1,4 @@
include $(VHDL_HOME)/make/defs.mk include $(VHDL_MAKE_HOME)/defs.mk
include $(LIB_PATH)/FIFO/ghdl/fifo_sync.inc include $(LIB_PATH)/FIFO/ghdl/fifo_sync.inc
include $(LIB_PATH)/filter/ghdl/fir_semi_parallel.inc include $(LIB_PATH)/filter/ghdl/fir_semi_parallel.inc
@@ -22,5 +22,5 @@ WAVE_FORMAT := vcd
GHDL_OPTS := -P$(LIB_PATH)/fixed/ieee_proposed/build/fixed_pkg/ieee_proposed GHDL_OPTS := -P$(LIB_PATH)/fixed/ieee_proposed/build/fixed_pkg/ieee_proposed
include $(VHDL_HOME)/make/ghdl.mk include $(VHDL_MAKE_HOME)/ghdl.mk
lib/radio/ddc/ghdl/tb_syn_ddc.make
+2 -2
View File
@@ -1,4 +1,4 @@
include $(VHDL_HOME)/make/defs.mk include $(VHDL_MAKE_HOME)/defs.mk
include $(LIB_PATH)/FIFO/ghdl/fifo_sync.inc include $(LIB_PATH)/FIFO/ghdl/fifo_sync.inc
include $(LIB_PATH)/FIFO/ghdl/fifo_async.inc include $(LIB_PATH)/FIFO/ghdl/fifo_async.inc
@@ -26,5 +26,5 @@ WAVE_FORMAT := vcd
GHDL_OPTS := -P$(LIB_PATH)/fixed/ieee_proposed/build/fixed_pkg/ieee_proposed GHDL_OPTS := -P$(LIB_PATH)/fixed/ieee_proposed/build/fixed_pkg/ieee_proposed
include $(VHDL_HOME)/make/ghdl.mk include $(VHDL_MAKE_HOME)/ghdl.mk
lib/radio/decimator/CIC/ghdl/cic_decim_pipe.inc
+1 -1
View File
@@ -1,5 +1,5 @@
# ----------------------------------------------------------- # -----------------------------------------------------------
include $(VHDL_HOME)/make/defs.mk include $(VHDL_MAKE_HOME)/defs.mk
# ----------------------------------------------------------- # -----------------------------------------------------------
PKG_NAME := CIC_DECIM_PIPE PKG_NAME := CIC_DECIM_PIPE
lib/radio/decimator/CIC/ghdl/tb_cic_decim_pipe.make
+2 -2
View File
@@ -1,4 +1,4 @@
include $(VHDL_HOME)/make/defs.mk include $(VHDL_MAKE_HOME)/defs.mk
include cic_decim_pipe.inc include cic_decim_pipe.inc
SRCS += $(CIC_DECIM_PIPE_SRCS) SRCS += $(CIC_DECIM_PIPE_SRCS)
@@ -14,5 +14,5 @@ WAVE_FORMAT := vcd
GHDL_OPTS := -P$(LIB_PATH)/fixed/ieee_proposed/build/fixed_pkg/ieee_proposed GHDL_OPTS := -P$(LIB_PATH)/fixed/ieee_proposed/build/fixed_pkg/ieee_proposed
include $(VHDL_HOME)/make/ghdl.mk include $(VHDL_MAKE_HOME)/ghdl.mk
lib/radio/nco/ghdl/mix_cordic_pipe.inc
+1 -1
View File
@@ -1,5 +1,5 @@
# ----------------------------------------------------------- # -----------------------------------------------------------
include $(VHDL_HOME)/make/defs.mk include $(VHDL_MAKE_HOME)/defs.mk
include $(LIB_PATH)/radio/cordic/ghdl/cordic_pipe.inc include $(LIB_PATH)/radio/cordic/ghdl/cordic_pipe.inc
# ----------------------------------------------------------- # -----------------------------------------------------------
PKG_NAME := MIX_CORDIC_PIPE PKG_NAME := MIX_CORDIC_PIPE
lib/radio/nco/ghdl/nco_lut.inc
+1 -1
View File
@@ -1,5 +1,5 @@
# ----------------------------------------------------------- # -----------------------------------------------------------
include $(VHDL_HOME)/make/defs.mk include $(VHDL_MAKE_HOME)/defs.mk
# ----------------------------------------------------------- # -----------------------------------------------------------
PKG_NAME := NCO_LUT PKG_NAME := NCO_LUT
lib/radio/nco/ghdl/tb_mix_cordic.make
+2 -2
View File
@@ -1,5 +1,5 @@
# ------------------------------------------------- # -------------------------------------------------
include $(VHDL_HOME)/make/defs.mk include $(VHDL_MAKE_HOME)/defs.mk
include $(LIB_PATH)/radio/nco/ghdl/mix_cordic_pipe.inc include $(LIB_PATH)/radio/nco/ghdl/mix_cordic_pipe.inc
# ------------------------------------------------- # -------------------------------------------------
@@ -26,7 +26,7 @@ WAVE_FORMAT := vcd
GHDL_OPTS := -P$(LIB_PATH)/fixed/ieee_proposed/build/fixed_pkg/ieee_proposed GHDL_OPTS := -P$(LIB_PATH)/fixed/ieee_proposed/build/fixed_pkg/ieee_proposed
include $(VHDL_HOME)/make/ghdl.mk include $(VHDL_MAKE_HOME)/ghdl.mk
# ------------------------------------------------- # -------------------------------------------------
lib/radio/nco/ghdl/tb_nco_cordic.make
+2 -2
View File
@@ -1,5 +1,5 @@
# ------------------------------------------------- # -------------------------------------------------
include $(VHDL_HOME)/make/defs.mk include $(VHDL_MAKE_HOME)/defs.mk
include $(LIB_PATH)/radio/nco/ghdl/mix_cordic_pipe.inc include $(LIB_PATH)/radio/nco/ghdl/mix_cordic_pipe.inc
# ------------------------------------------------- # -------------------------------------------------
@@ -26,7 +26,7 @@ WAVE_FORMAT := vcd
GHDL_OPTS := -P$(LIB_PATH)/fixed/ieee_proposed/build/fixed_pkg/ieee_proposed GHDL_OPTS := -P$(LIB_PATH)/fixed/ieee_proposed/build/fixed_pkg/ieee_proposed
include $(VHDL_HOME)/make/ghdl.mk include $(VHDL_MAKE_HOME)/ghdl.mk
# ------------------------------------------------- # -------------------------------------------------
lib/radio/nco/ghdl/tb_nco_lut.make
+2 -2
View File
@@ -1,5 +1,5 @@
# ------------------------------------------------- # -------------------------------------------------
include $(VHDL_HOME)/make/defs.mk include $(VHDL_MAKE_HOME)/defs.mk
include $(LIB_PATH)/radio/nco/ghdl/nco_lut.inc include $(LIB_PATH)/radio/nco/ghdl/nco_lut.inc
# ------------------------------------------------- # -------------------------------------------------
@@ -26,6 +26,6 @@ WAVE_FORMAT := vcd
GHDL_OPTS := -P$(LIB_PATH)/fixed/ieee_proposed/build/fixed_pkg/ieee_proposed GHDL_OPTS := -P$(LIB_PATH)/fixed/ieee_proposed/build/fixed_pkg/ieee_proposed
include $(VHDL_HOME)/make/ghdl.mk include $(VHDL_MAKE_HOME)/ghdl.mk
# ------------------------------------------------- # -------------------------------------------------
lib/uart/ghdl/tb_uart_generic.make
+2 -2
View File
@@ -1,5 +1,5 @@
# ----------------------------------------------------------- # -----------------------------------------------------------
include $(VHDL_HOME)/make/defs.mk include $(VHDL_MAKE_HOME)/defs.mk
# ----------------------------------------------------------- # -----------------------------------------------------------
include $(VHDL_HOME)/lib/uart/ghdl/uart_generic.inc include $(VHDL_HOME)/lib/uart/ghdl/uart_generic.inc
@@ -15,6 +15,6 @@ TARGET := tb_uart_generic
ENTITY := tb_uart ENTITY := tb_uart
RUN_TIME := 880us RUN_TIME := 880us
include $(VHDL_HOME)/make/ghdl.mk include $(VHDL_MAKE_HOME)/ghdl.mk
# ----------------------------------------------------------- # -----------------------------------------------------------
lib/uart/ghdl/tb_uart_sim.make
+2 -2
View File
@@ -1,5 +1,5 @@
# ----------------------------------------------------------- # -----------------------------------------------------------
include $(VHDL_HOME)/make/defs.mk include $(VHDL_MAKE_HOME)/defs.mk
# ----------------------------------------------------------- # -----------------------------------------------------------
include $(VHDL_HOME)/lib/uart/ghdl/uart_sim.inc include $(VHDL_HOME)/lib/uart/ghdl/uart_sim.inc
@@ -15,6 +15,6 @@ TARGET := tb_uart_sim
ENTITY := tb_uart ENTITY := tb_uart
RUN_TIME := 880us RUN_TIME := 880us
include $(VHDL_HOME)/make/ghdl.mk include $(VHDL_MAKE_HOME)/ghdl.mk
# ----------------------------------------------------------- # -----------------------------------------------------------
lib/uart/ghdl/uart_generic.inc
+1 -1
View File
@@ -1,5 +1,5 @@
# ----------------------------------------------------------- # -----------------------------------------------------------
include $(VHDL_HOME)/make/defs.mk include $(VHDL_MAKE_HOME)/defs.mk
# ----------------------------------------------------------- # -----------------------------------------------------------
PKG_NAME := UART_GENERIC PKG_NAME := UART_GENERIC
lib/uart/ghdl/uart_sim.inc
+1 -1
View File
@@ -1,5 +1,5 @@
# ----------------------------------------------------------- # -----------------------------------------------------------
include $(VHDL_HOME)/make/defs.mk include $(VHDL_MAKE_HOME)/defs.mk
# ----------------------------------------------------------- # -----------------------------------------------------------
PKG_NAME := UART_SIM PKG_NAME := UART_SIM