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Refactored after moving of VHDL make

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jens
2022-09-07 13:09:41 +02:00
parent cbc093e6e7
commit d3beeb0538
63 changed files with 94 additions and 94 deletions
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lib/uart/ghdl/tb_uart_sim.make
+2 -2
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@@ -1,5 +1,5 @@
# -----------------------------------------------------------
include $(VHDL_HOME)/make/defs.mk
include $(VHDL_MAKE_HOME)/defs.mk
# -----------------------------------------------------------
include $(VHDL_HOME)/lib/uart/ghdl/uart_sim.inc
@@ -15,6 +15,6 @@ TARGET := tb_uart_sim
ENTITY := tb_uart
RUN_TIME := 880us
include $(VHDL_HOME)/make/ghdl.mk
include $(VHDL_MAKE_HOME)/ghdl.mk
# -----------------------------------------------------------