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Refactored after moving of VHDL make

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This commit is contained in:
jens
2022-09-07 13:09:41 +02:00
parent cbc093e6e7
commit d3beeb0538
63 changed files with 94 additions and 94 deletions
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lib/filter/ghdl/fir_iterative.inc
+1 -1
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@@ -1,5 +1,5 @@
# -----------------------------------------------------------
include $(VHDL_HOME)/make/defs.mk
include $(VHDL_MAKE_HOME)/defs.mk
# -----------------------------------------------------------
PKG_NAME := FIR_ITERATIVE
lib/filter/ghdl/fir_parallel.inc
+1 -1
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@@ -1,5 +1,5 @@
# -----------------------------------------------------------
include $(VHDL_HOME)/make/defs.mk
include $(VHDL_MAKE_HOME)/defs.mk
# -----------------------------------------------------------
PKG_NAME := FIR_PARALLEL
lib/filter/ghdl/fir_semi_parallel.inc
+1 -1
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@@ -1,5 +1,5 @@
# -----------------------------------------------------------
include $(VHDL_HOME)/make/defs.mk
include $(VHDL_MAKE_HOME)/defs.mk
# -----------------------------------------------------------
PKG_NAME := FIR_SEMI_PARALLEL
lib/filter/ghdl/tb_fir_iterative.make
+2 -2
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@@ -1,4 +1,4 @@
include $(VHDL_HOME)/make/defs.mk
include $(VHDL_MAKE_HOME)/defs.mk
include fir_iterative.inc
ROOT_PATH := ../../..
@@ -15,5 +15,5 @@ ENTITY := tb_fir_iterative
GHDL_OPTS := -P$(LIB_PATH)/fixed/ieee_proposed/build/fixed_pkg/ieee_proposed
RUN_TIME := 6us
include $(VHDL_HOME)/make/ghdl.mk
include $(VHDL_MAKE_HOME)/ghdl.mk
lib/filter/ghdl/tb_fir_parallel.make
+2 -2
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@@ -1,4 +1,4 @@
include $(VHDL_HOME)/make/defs.mk
include $(VHDL_MAKE_HOME)/defs.mk
include fir_parallel.inc
ROOT_PATH := ../../..
@@ -15,5 +15,5 @@ ENTITY := tb_fir_parallel
GHDL_OPTS := -P$(LIB_PATH)/fixed/ieee_proposed/build/fixed_pkg/ieee_proposed
RUN_TIME := 200us
include $(VHDL_HOME)/make/ghdl.mk
include $(VHDL_MAKE_HOME)/ghdl.mk
lib/filter/ghdl/tb_fir_semi_parallel.make
+2 -2
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@@ -1,4 +1,4 @@
include $(VHDL_HOME)/make/defs.mk
include $(VHDL_MAKE_HOME)/defs.mk
include fir_semi_parallel.inc
ROOT_PATH := ../../..
@@ -15,5 +15,5 @@ ENTITY := tb_fir_semi_parallel
GHDL_OPTS := -P$(LIB_PATH)/fixed/ieee_proposed/build/fixed_pkg/ieee_proposed
RUN_TIME := 50us
include $(VHDL_HOME)/make/ghdl.mk
include $(VHDL_MAKE_HOME)/ghdl.mk
lib/filter/ghdl/tb_fir_stage.make
+2 -2
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@@ -1,4 +1,4 @@
include $(VHDL_HOME)/make/defs.mk
include $(VHDL_MAKE_HOME)/defs.mk
SRCS += $(LIB_PATH)/PCK_FIO-2002.7/PCK_FIO_1993.vhd
SRCS += $(LIB_PATH)/PCK_FIO-2002.7/PCK_FIO_1993_BODY.vhd
@@ -15,5 +15,5 @@ ENTITY := tb_fir_stage
GHDL_OPTS := -P$(LIB_PATH)/fixed/ieee_proposed/build/fixed_pkg/ieee_proposed
RUN_TIME := 2us
include $(VHDL_HOME)/make/ghdl.mk
include $(VHDL_MAKE_HOME)/ghdl.mk
lib/filter/ghdl/tb_fir_stage_sys.make
+2 -2
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@@ -1,4 +1,4 @@
include $(VHDL_HOME)/make/defs.mk
include $(VHDL_MAKE_HOME)/defs.mk
SRCS += $(LIB_PATH)/PCK_FIO-2002.7/PCK_FIO_1993.vhd
SRCS += $(LIB_PATH)/PCK_FIO-2002.7/PCK_FIO_1993_BODY.vhd
@@ -15,5 +15,5 @@ ENTITY := tb_fir_stage_sys
GHDL_OPTS := -P$(LIB_PATH)/fixed/ieee_proposed/build/fixed_pkg/ieee_proposed
RUN_TIME := 2us
include $(VHDL_HOME)/make/ghdl.mk
include $(VHDL_MAKE_HOME)/ghdl.mk