Refactored after moving of VHDL make

This commit is contained in:
2022-09-07 13:09:41 +02:00
parent cbc093e6e7
commit d3beeb0538
63 changed files with 94 additions and 94 deletions
+2 -2
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@@ -1,5 +1,5 @@
# -----------------------------------------------------------
include $(VHDL_HOME)/make/defs.mk
include $(VHDL_MAKE_HOME)/defs.mk
# -----------------------------------------------------------
include vga_frontend_jb32.inc
@@ -13,6 +13,6 @@ TARGET := tb_vga_frontend_jb32
ENTITY := tb_vga_frontend_jb32
RUN_TIME := 20ms
include $(VHDL_HOME)/make/ghdl.mk
include $(VHDL_MAKE_HOME)/ghdl.mk
# -----------------------------------------------------------
+2 -2
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@@ -1,5 +1,5 @@
# -----------------------------------------------------------
include $(VHDL_HOME)/make/defs.mk
include $(VHDL_MAKE_HOME)/defs.mk
# -----------------------------------------------------------
include vga_frontend_jb64.inc
@@ -13,6 +13,6 @@ TARGET := tb_vga_frontend_jb64
ENTITY := tb_vga_frontend_jb64
RUN_TIME := 2ms
include $(VHDL_HOME)/make/ghdl.mk
include $(VHDL_MAKE_HOME)/ghdl.mk
# -----------------------------------------------------------
+1 -1
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@@ -1,5 +1,5 @@
# -----------------------------------------------------------
include $(VHDL_HOME)/make/defs.mk
include $(VHDL_MAKE_HOME)/defs.mk
# -----------------------------------------------------------
PKG_NAME := VGA_BACKEND
+1 -1
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@@ -1,5 +1,5 @@
# -----------------------------------------------------------
include $(VHDL_HOME)/make/defs.mk
include $(VHDL_MAKE_HOME)/defs.mk
include vga_backend.inc
include $(LIB_PATH)/FIFO/ghdl/fifo_async.inc
+1 -1
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@@ -1,5 +1,5 @@
# -----------------------------------------------------------
include $(VHDL_HOME)/make/defs.mk
include $(VHDL_MAKE_HOME)/defs.mk
include $(LIB_PATH)/VGA_ctrl/ghdl/vga_backend.inc
include $(LIB_PATH)/FIFO/ghdl/fifo_sync.inc
include $(LIB_PATH)/FIFO/ghdl/fifo_async.inc