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Refactored after moving of VHDL make

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jens
2022-09-07 13:09:41 +02:00
parent cbc093e6e7
commit d3beeb0538
63 changed files with 94 additions and 94 deletions
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lib/SDRAM/ddr_sdr_v1_5/ghdl/tb_ctrl_ddr_wb32.make
+2 -2
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@@ -1,5 +1,5 @@
# -----------------------------------------------------------
include $(VHDL_HOME)/make/defs.mk
include $(VHDL_MAKE_HOME)/defs.mk
# -----------------------------------------------------------
include $(LIB_PATH)/FIFO/ghdl/fifo_sync.inc
include $(LIB_PATH)/FIFO/ghdl/fifo_async.inc
@@ -31,5 +31,5 @@ WAVE_FORMAT := vcd
GHDL_OPTS := -P$(VHDL_HOME)/Common/sim/build/ghdl/unisim -fsynopsys -fexplicit
include $(VHDL_HOME)/make/ghdl.mk
include $(VHDL_MAKE_HOME)/ghdl.mk
lib/SDRAM/ddr_sdr_v1_5/ghdl/tb_ctrl_ddr_wb64.make
+2 -2
View File
@@ -1,5 +1,5 @@
# -----------------------------------------------------------
include $(VHDL_HOME)/make/defs.mk
include $(VHDL_MAKE_HOME)/defs.mk
# -----------------------------------------------------------
include $(LIB_PATH)/FIFO/ghdl/fifo_sync.inc
include $(LIB_PATH)/FIFO/ghdl/fifo_async.inc
@@ -30,5 +30,5 @@ WAVE_FORMAT := vcd
GHDL_OPTS := -P$(VHDL_HOME)/Common/sim/build/ghdl/unisim -fsynopsys -fexplicit
include $(VHDL_HOME)/make/ghdl.mk
include $(VHDL_MAKE_HOME)/ghdl.mk