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Refactored after moving of VHDL make

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This commit is contained in:
jens
2022-09-07 13:09:41 +02:00
parent cbc093e6e7
commit d3beeb0538
63 changed files with 94 additions and 94 deletions
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lib/JBUS/memory/ghdl/tb_ram_wb.make
+2 -2
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@@ -1,4 +1,4 @@
include $(VHDL_HOME)/make/defs.mk
include $(VHDL_MAKE_HOME)/defs.mk
MOD_PATH := $(LIB_PATH)/JBUS/memory
@@ -13,4 +13,4 @@ ENTITY := tb_ram_wb
RUN_TIME := 1500ns
WAVE_FORMAT := vcd
include $(VHDL_HOME)/make/ghdl.mk
include $(VHDL_MAKE_HOME)/ghdl.mk
lib/JBUS/memory/ghdl/tb_rom_wb.make
+2 -2
View File
@@ -1,4 +1,4 @@
include $(VHDL_HOME)/make/defs.mk
include $(VHDL_MAKE_HOME)/defs.mk
MOD_PATH := $(LIB_PATH)/JBUS/memory
@@ -12,5 +12,5 @@ ENTITY := tb_rom_wb
RUN_TIME := 1500ns
WAVE_FORMAT := vcd
include $(VHDL_HOME)/make/ghdl.mk
include $(VHDL_MAKE_HOME)/ghdl.mk