Refactored after moving of VHDL make

2022-09-07 13:09:41 +02:00
parent cbc093e6e7
commit d3beeb0538
63 changed files with 94 additions and 94 deletions
@@ -1,4 +1,4 @@
-include $(VHDL_HOME)/make/defs.mk
+include $(VHDL_MAKE_HOME)/defs.mk
 include $(LIB_PATH)/FIFO/ghdl/fifo_sync.inc

 MOD_PATH := $(LIB_PATH)/JBUS
@@ -16,5 +16,5 @@ ENTITY := tb_dmac
 RUN_TIME := 6us
 WAVE_FORMAT := vcd

-include $(VHDL_HOME)/make/ghdl.mk
+include $(VHDL_MAKE_HOME)/ghdl.mk