Refactored after moving of VHDL make

This commit is contained in:
2022-09-07 13:09:41 +02:00
parent cbc093e6e7
commit d3beeb0538
63 changed files with 94 additions and 94 deletions
+1 -1
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@@ -1,5 +1,5 @@
# -----------------------------------------------------------
include $(VHDL_HOME)/make/defs.mk
include $(VHDL_MAKE_HOME)/defs.mk
# -----------------------------------------------------------
PKG_NAME := FIFO_ASYNC
+1 -1
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@@ -1,5 +1,5 @@
# -----------------------------------------------------------
include $(VHDL_HOME)/make/defs.mk
include $(VHDL_MAKE_HOME)/defs.mk
# -----------------------------------------------------------
PKG_NAME := FIFO_SYNC
+2 -2
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@@ -1,4 +1,4 @@
include $(VHDL_HOME)/make/defs.mk
include $(VHDL_MAKE_HOME)/defs.mk
include fifo_async.inc
ROOT_PATH := ../../..
@@ -12,5 +12,5 @@ TARGET := tb_fifo_async
ENTITY := tb_fifo_async
RUN_TIME := 5us
include $(VHDL_HOME)/make/ghdl.mk
include $(VHDL_MAKE_HOME)/ghdl.mk
+2 -2
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@@ -1,4 +1,4 @@
include $(VHDL_HOME)/make/defs.mk
include $(VHDL_MAKE_HOME)/defs.mk
include fifo_sync.inc
ROOT_PATH := ../../..
@@ -12,5 +12,5 @@ TARGET := tb_fifo_sync
ENTITY := tb_fifo_sync
RUN_TIME := 5us
include $(VHDL_HOME)/make/ghdl.mk
include $(VHDL_MAKE_HOME)/ghdl.mk
+2 -2
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@@ -1,4 +1,4 @@
include $(VHDL_HOME)/make/defs.mk
include $(VHDL_MAKE_HOME)/defs.mk
SRCS += $(LIB_PATH)/FIFO/src/fifo_ctrl_pkg.vhd
SRCS += $(LIB_PATH)/FIFO/src/gray_counter.vhd
@@ -9,5 +9,5 @@ TARGET := tb_gray_counter
ENTITY := tb_gray_counter
RUN_TIME := 1us
include $(VHDL_HOME)/make/ghdl.mk
include $(VHDL_MAKE_HOME)/ghdl.mk
+2 -2
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@@ -1,4 +1,4 @@
include $(VHDL_HOME)/make/defs.mk
include $(VHDL_MAKE_HOME)/defs.mk
SRCS += $(LIB_PATH)/FIFO/src/reg_stage.vhd
SRCS += $(LIB_PATH)/FIFO/src/tb_reg_stage.vhd
@@ -8,5 +8,5 @@ TARGET := tb_reg_stage
ENTITY := tb_reg_stage
RUN_TIME := 1us
include $(VHDL_HOME)/make/ghdl.mk
include $(VHDL_MAKE_HOME)/ghdl.mk