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- some performance improvements

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git-svn-id: http://moon:8086/svn/vhdl/trunk@567 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
jens
2009-10-30 13:51:00 +00:00
parent a38101e448
commit d37afef047
1 changed files with 6 additions and 5 deletions
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lib/misc/async_port_wb.vhd
+6 -5
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@@ -1,5 +1,5 @@
----------------------------------------------------------------------- -----------------------------------------------------------------------
-- $Header: /tmp/cvsroot/VHDL/lib/misc/async_port_wb.vhd,v 1.10 2009-10-30 12:26:42 Jens Exp $ -- $Header: /tmp/cvsroot/VHDL/lib/misc/async_port_wb.vhd,v 1.11 2009-10-30 13:51:00 Jens Exp $
----------------------------------------------------------------------- -----------------------------------------------------------------------
library IEEE; library IEEE;
use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_1164.ALL;
@@ -182,7 +182,9 @@ architecture Behavioral of async_port_wb is
cycle_reload <= async_timespec.ncyc_pulse_page_rd-1; cycle_reload <= async_timespec.ncyc_pulse_page_rd-1;
sn <= pulse; sn <= pulse;
elsif async_timespec.ncyc_leadout = 0 then elsif async_timespec.ncyc_leadout = 0 then
if async_timespec.ncyc_release = 0 then if en = '1' and (WE_I = WE_I_r) then
sn <= idle;
elsif async_timespec.ncyc_release = 0 then
sn <= idle; sn <= idle;
else else
cycle_reload <= async_timespec.ncyc_release-1; cycle_reload <= async_timespec.ncyc_release-1;
@@ -198,8 +200,7 @@ architecture Behavioral of async_port_wb is
as.cs <= '1'; as.cs <= '1';
if cycle_cnt = 0 then if cycle_cnt = 0 then
cc_rst <= '1'; cc_rst <= '1';
rdy <= '1'; if en = '1' and (WE_I = WE_I_r) then
if en = '1' then
sn <= idle; sn <= idle;
elsif async_timespec.ncyc_release = 0 then elsif async_timespec.ncyc_release = 0 then
sn <= idle; sn <= idle;
@@ -226,7 +227,6 @@ architecture Behavioral of async_port_wb is
begin begin
if rising_edge(CLK_I) then if rising_edge(CLK_I) then
async_cs <= (not async_timespec.pol_cs) xor as.cs; async_cs <= (not async_timespec.pol_cs) xor as.cs;
async_be <= (byte_sel_width-1 downto 0 => not async_timespec.pol_be) xor ((byte_sel_width-1 downto 0 => as.cs) and SEL_I_r);
async_wr <= (not async_timespec.pol_we) xor as.wr; async_wr <= (not async_timespec.pol_we) xor as.wr;
async_rd <= (not async_timespec.pol_oe) xor as.rd; async_rd <= (not async_timespec.pol_oe) xor as.rd;
async_rst <= (not async_timespec.pol_rst) xor as.rst; async_rst <= (not async_timespec.pol_rst) xor as.rst;
@@ -254,6 +254,7 @@ architecture Behavioral of async_port_wb is
SEL_I_r <= (others => '0'); SEL_I_r <= (others => '0');
elsif en = '1' and rdy = '1' then elsif en = '1' and rdy = '1' then
async_a <= ADDR_I(addr_width-1 downto 0); async_a <= ADDR_I(addr_width-1 downto 0);
async_be <= (byte_sel_width-1 downto 0 => not async_timespec.pol_be) xor ((byte_sel_width-1 downto 0 => as.cs) and SEL_I);
SEL_I_r <= SEL_I(byte_sel_width-1 downto 0); SEL_I_r <= SEL_I(byte_sel_width-1 downto 0);
if is_idle = '1' then if is_idle = '1' then
ADDR_I_r <= ADDR_I(addr_width-1 downto 0); ADDR_I_r <= ADDR_I(addr_width-1 downto 0);