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- added Altera stuff

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git-svn-id: http://moon:8086/svn/vhdl/trunk@772 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
jens
2010-03-12 07:41:16 +00:00
parent 22024a75df
commit d30f067cee
2 changed files with 308 additions and 30 deletions
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lib/radio/ddc/src/tb_ddc.vhd
+7 -5
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@@ -33,13 +33,13 @@ ENTITY tb_ddc IS
nbits_in_frac : integer := 14;
nbits_out : integer := 32;
nbits_out_frac : integer := 30;
lo_nbits_phase : integer := 20;
lo_nbits_freq : integer := 20;
lo_nbits_phase : integer := 24;
lo_nbits_freq : integer := 24;
cic_nstages : integer := 5;
cic_ratio : integer := 25;
cic_scale_nbits : integer := 22;
rfgen_nbits_phase : integer := 20;
rfgen_nbits_freq : integer := 20
rfgen_nbits_phase : integer := 32;
rfgen_nbits_freq : integer := 32
);
END tb_ddc;
@@ -108,7 +108,7 @@ ARCHITECTURE behavior OF tb_ddc IS
END COMPONENT;
--Constants
constant fa : REAL := 100.0E6;
constant fa : REAL := 2.0**27;
constant frf1 : REAL := 33.99E6;
constant frf2 : REAL := 2.1E6;
constant frf3 : REAL := 19.01E6;
@@ -352,6 +352,7 @@ BEGIN
tb_param : PROCESS
file RESULT_R: text open write_mode is "ratio.txt";
file RESULT_N: text open write_mode is "nstages.txt";
file FSAMPLE: text open write_mode is "fa.txt";
variable L: line;
BEGIN
@@ -360,6 +361,7 @@ BEGIN
wait until rising_edge(clk) and rst = '0';
fprint(RESULT_R, L,"%s\n", natural'image(cic_ratio));
fprint(RESULT_N, L,"%s\n", natural'image(cic_nstages));
fprint(FSAMPLE, L,"%s\n", real'image(fa));
wait;
END PROCESS;