- added Altera stuff
Committed on the Free edition of March Hare Software CVSNT Server. Upgrade to CVS Suite for more features and support: http://march-hare.com/cvsnt/ git-svn-id: http://moon:8086/svn/vhdl/trunk@772 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
+301
-25
@@ -20,6 +20,9 @@ library ieee_proposed;
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use ieee_proposed.math_utility_pkg.all;
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use ieee_proposed.fixed_pkg.all;
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library altera;
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use altera.altera_syn_attributes.all;
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library work;
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use work.fixed_util_pkg.all;
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@@ -30,26 +33,51 @@ use work.fixed_util_pkg.all;
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nbits_in_frac : integer := 14;
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nbits_out : integer := 32;
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nbits_out_frac : integer := 30;
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lo_nbits_phase : integer := 20;
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lo_nbits_freq : integer := 20;
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lo_nbits_phase : integer := 24;
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lo_nbits_freq : integer := 24;
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cic_nstages : integer := 5;
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cic_ratio : integer := 25;
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cic_scale_nbits : integer := 22
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);
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PORT
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(
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rst : in std_logic;
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clk : in std_logic;
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lo_nco_rst : in std_logic;
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lo_nco_en : in std_logic;
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lo_freq_in : in unsigned(lo_nbits_freq-1 downto 0);
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lo_phase_in : in unsigned(lo_nbits_phase-1 downto 0);
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din_i : in signed(nbits_in-1 downto 0);
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din_q : in signed(nbits_in-1 downto 0);
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dout_i : out signed(nbits_out-1 downto 0);
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dout_q : out signed(nbits_out-1 downto 0);
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din_vld : in std_logic;
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dout_vld : out std_logic
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rst : in std_logic;
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adc_clk : in std_logic;
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adc_da : in signed(15 downto 0);
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adc_ofa : in std_logic;
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adc_rand : out std_logic;
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adc_pga : out std_logic;
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adc_dith : out std_logic;
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adc_shdn : out std_logic;
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usb_usbclk : in std_logic;
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usb_ifclk : in std_logic;
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usb_fd : out signed(15 downto 0);
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usb_pktend : out std_logic;
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usb_fifoadr : out unsigned(1 downto 0);
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usb_slcs_n : out std_logic;
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usb_slwr_n : out std_logic;
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usb_slrd_n : out std_logic;
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usb_sloe : out std_logic;
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usb_flaga : in std_logic;
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usb_flagb : in std_logic;
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usb_flagc : in std_logic;
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cl_clk_out : out std_logic;
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cl_dout : out unsigned(23 downto 0);
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cl_pat_sel : out std_logic;
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cl_prbs_en : out std_logic;
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cl_ds_opt : out std_logic;
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cl_bal : out std_logic;
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cl_pd_n : out std_logic;
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cl_tsen : in std_logic;
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reg_aen : in std_logic;
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reg_dio : inout unsigned(7 downto 0);
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reg_oe : in std_logic;
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reg_we : in std_logic
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);
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END syn_ddc;
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@@ -99,6 +127,45 @@ ARCHITECTURE behavior OF syn_ddc IS
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SIGNAL ddc_dec_i : sfixed(shi(nbits_out, nbits_out_frac) downto slo(nbits_out, nbits_out_frac));
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SIGNAL ddc_dec_q : sfixed(shi(nbits_out, nbits_out_frac) downto slo(nbits_out, nbits_out_frac));
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SIGNAL reg_lo_nco_rst : std_logic;
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SIGNAL reg_lo_nco_en : std_logic;
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SIGNAL reg_lo_freq_in : unsigned(31 downto 0);
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SIGNAL reg_lo_phase_in : unsigned(31 downto 0);
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SIGNAL reg_en_addr : std_logic;
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SIGNAL reg_en_data : std_logic;
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SIGNAL reg_addr_last : std_logic;
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SIGNAL reg_data_last : std_logic;
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SIGNAL reg_addr_async : unsigned (7 downto 0);
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SIGNAL reg_data_async : unsigned (7 downto 0);
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SIGNAL reg_addr : unsigned (7 downto 0);
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SIGNAL reg_data : unsigned (7 downto 0);
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SIGNAL fifo_usb_we : std_logic;
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SIGNAL fifo_usb_re : std_logic;
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SIGNAL fifo_usb_ff : std_logic;
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SIGNAL fifo_usb_ef : std_logic;
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SIGNAL fifo_usb_aff : std_logic;
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SIGNAL fifo_usb_aef : std_logic;
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type fifo_usb_array_t is array (0 to 3) of unsigned (15 downto 0);
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SIGNAL fifo_usb_in : fifo_usb_array_t;
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SIGNAL fifo_usb_out : unsigned (15 downto 0);
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SIGNAL fifo_usb_we_pipe : unsigned(3 downto 0);
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SIGNAL enable : std_logic;
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SIGNAL ddc_din_vld : std_logic;
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SIGNAL ddc_dout_vld : std_logic;
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SIGNAL cl_we_pipe : unsigned(1 downto 0);
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type cl_data_array_t is array (0 to 1) of unsigned (31 downto 0);
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SIGNAL cl_sd_data : cl_data_array_t;
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SIGNAL cl_dout_L : std_logic_vector(24 downto 0);
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SIGNAL cl_dout_H : std_logic_vector(24 downto 0);
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SIGNAL cl_dout_clk : std_logic_vector(24 downto 0);
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BEGIN
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-- Instantiate the Unit Under Test (UUT)
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@@ -118,26 +185,235 @@ BEGIN
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PORT MAP
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(
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rst => rst,
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clk => clk,
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lo_nco_rst => lo_nco_rst,
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lo_nco_en => lo_nco_en,
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lo_freq_in => lo_freq_in,
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lo_phase_in => lo_phase_in,
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din_vld => din_vld,
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clk => adc_clk,
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lo_nco_rst => reg_lo_nco_rst,
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lo_nco_en => reg_lo_nco_en,
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lo_freq_in => reg_lo_freq_in(lo_nbits_freq-1 downto 0),
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lo_phase_in => reg_lo_phase_in(lo_nbits_phase-1 downto 0),
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din_vld => ddc_din_vld,
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din_i => ddc_din_i,
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din_q => ddc_din_q,
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dec_vld => dec_vld,
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dec_i => ddc_dec_i,
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dec_q => ddc_dec_q,
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dout_vld => dout_vld,
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dout_vld => ddc_dout_vld,
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dout_i => ddc_dout_i,
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dout_q => ddc_dout_q
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);
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reg_dio <= reg_addr when reg_oe = '1' else (others => 'Z');
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----------------------------------------------------------
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-- Register control
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----------------------------------------------------------
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proc_reg_da_async:
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process(reg_we)
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begin
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if rising_edge(reg_we) then
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if reg_aen = '1' then
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reg_addr_async <= reg_dio;
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else
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reg_data_async <= reg_dio;
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end if;
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end if;
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end process;
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ddc_din_i <= sfixed(din_i);
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ddc_din_q <= sfixed(din_q);
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proc_reg_da_sync:
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process(adc_clk)
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-- process(usb_usbclk)
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begin
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if rising_edge(adc_clk) then
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-- if rising_edge(usb_usbclk) then
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if rst = '1' then
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reg_en_addr <= '0';
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reg_en_data <= '0';
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reg_addr_last <= '0';
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reg_data_last <= '0';
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elsif reg_we = '1' then
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reg_en_addr <= reg_aen and not reg_addr_last;
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reg_en_data <= not (reg_aen or reg_data_last);
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reg_addr_last <= reg_aen;
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reg_data_last <= not reg_aen;
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else
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reg_addr_last <= '0';
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reg_data_last <= '0';
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end if;
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reg_data <= reg_data_async;
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reg_addr <= reg_addr_async;
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end if;
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end process;
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-- Registers
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proc_register_write:
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process(adc_clk)
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-- process(usb_usbclk)
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begin
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if rising_edge(adc_clk) then
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-- if rising_edge(usb_usbclk) then
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if rst = '1' then
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reg_lo_nco_rst <= '0';
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reg_lo_nco_en <= '0';
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elsif reg_en_data = '1' then
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case reg_addr is
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when X"00" => -- Control
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reg_lo_nco_rst <= reg_data(0);
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reg_lo_nco_en <= reg_data(1);
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when X"10" => -- freqency
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reg_lo_freq_in(7 downto 0) <= reg_data;
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when X"11" => -- freqency
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reg_lo_freq_in(15 downto 8) <= reg_data;
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when X"12" => -- freqency
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reg_lo_freq_in(23 downto 16) <= reg_data;
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when X"13" => -- freqency
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reg_lo_freq_in(31 downto 24) <= reg_data;
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when X"20" => -- phase
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reg_lo_phase_in(7 downto 0) <= reg_data;
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when X"21" => -- phase
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reg_lo_phase_in(15 downto 8) <= reg_data;
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when X"22" => -- phase
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reg_lo_phase_in(23 downto 16) <= reg_data;
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when X"23" => -- phase
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reg_lo_phase_in(31 downto 24) <= reg_data;
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when others => null;
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end case;
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end if;
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end if;
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end process;
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----------------------------------------------------------
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-- DDC input
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----------------------------------------------------------
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proc_adc_input_register:
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process(adc_clk)
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begin
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if rising_edge(adc_clk) then
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ddc_din_vld <= enable;
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if enable = '1' then
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ddc_din_i <= sfixed(resize(adc_da, nbits_in));
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end if;
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end if;
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end process;
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ddc_din_q <= to_sfixed(0.0, shi(nbits_in, nbits_in_frac), slo(nbits_in, nbits_in_frac));
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dout_i <= signed(ddc_dout_i);
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dout_q <= signed(ddc_dout_q);
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enable <= '1';
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adc_rand <= '0';
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adc_pga <= '0';
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adc_dith <= '0';
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adc_shdn <= not enable;
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----------------------------------------------------------
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-- USB FIFO output
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----------------------------------------------------------
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proc_usb_interleave_iq:
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process(adc_clk)
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variable i, q : unsigned(31 downto 0);
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begin
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if rising_edge(adc_clk) then
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if rst = '1' then
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fifo_usb_we_pipe <= (others => '0');
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elsif ddc_dout_vld = '1' then
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fifo_usb_we_pipe <= (others => '1');
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i := unsigned(ddc_dout_i);
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q := unsigned(ddc_dout_q);
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fifo_usb_in(0) <= i(15 downto 0);
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fifo_usb_in(1) <= i(31 downto 16);
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fifo_usb_in(2) <= q(15 downto 0);
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fifo_usb_in(3) <= q(31 downto 16);
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elsif fifo_usb_ff = '0' then
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fifo_usb_we_pipe <= fifo_usb_we_pipe(fifo_usb_we_pipe'left-1 downto 0) & '0';
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fifo_usb_in(0) <= fifo_usb_in(1);
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fifo_usb_in(1) <= fifo_usb_in(2);
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fifo_usb_in(2) <= fifo_usb_in(3);
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end if;
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end if;
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end process;
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inst_usbfifo: entity work.fifo_async
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GENERIC MAP
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(
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addr_width => 7,
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data_width => 16,
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almost_full_thresh => 96,
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almost_empty_thresh => 32
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)
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PORT MAP
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(
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rst => rst,
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clk_w => adc_clk,
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clk_r => usb_ifclk,
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we => fifo_usb_we,
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re => fifo_usb_re,
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data_w => fifo_usb_in(0),
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data_r => fifo_usb_out,
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fifo_full => fifo_usb_ff,
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fifo_empty => fifo_usb_ef,
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fifo_afull => fifo_usb_aff,
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fifo_aempty => fifo_usb_aef
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);
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fifo_usb_we <= fifo_usb_we_pipe(fifo_usb_we_pipe'left);
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usb_fd <= signed(fifo_usb_out);
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fifo_usb_re <= usb_flaga;
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usb_slcs_n <= '0';
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usb_slwr_n <= not usb_flaga;
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usb_slrd_n <= '1';
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usb_sloe <= '0';
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----------------------------------------------------------
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-- Channel-Link DDR output
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----------------------------------------------------------
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proc_cl_interleave_iq:
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process(adc_clk)
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variable i, q : unsigned(31 downto 0);
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begin
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if rising_edge(adc_clk) then
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if rst = '1' then
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cl_we_pipe <= (others => '0');
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elsif ddc_dout_vld = '1' then
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cl_we_pipe <= (others => '1');
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i := unsigned(ddc_dout_i);
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q := unsigned(ddc_dout_q);
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cl_sd_data(0) <= i;
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cl_sd_data(1) <= q;
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else
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cl_we_pipe <= cl_we_pipe(cl_we_pipe'left-1 downto 0) & '0';
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cl_sd_data(0) <= cl_sd_data(1);
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end if;
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end if;
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end process;
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inst_cl_ddr_out: entity work.cl_ddr_out
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PORT MAP
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(
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aclr => rst,
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datain_h => cl_dout_H,
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datain_l => cl_dout_L,
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outclock => adc_clk,
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outclocken => '1',
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dataout => cl_dout_clk
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);
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cl_dout_H <= '0' & cl_we_pipe(cl_we_pipe'left) & "0000000" & std_logic_vector(cl_sd_data(0)(31 downto 16));
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cl_dout_L <= '1' & cl_we_pipe(cl_we_pipe'left) & "0000000" & std_logic_vector(cl_sd_data(0)(15 downto 0));
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cl_dout <= unsigned(cl_dout_clk(23 downto 0));
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cl_clk_out <= cl_dout_clk(24);
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cl_pat_sel <= '0';
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cl_prbs_en <= '0';
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cl_ds_opt <= '0';
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cl_bal <= '0';
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cl_pd_n <= '1';
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----------------------------------------------------------
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END;
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@@ -33,13 +33,13 @@ ENTITY tb_ddc IS
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nbits_in_frac : integer := 14;
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nbits_out : integer := 32;
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nbits_out_frac : integer := 30;
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lo_nbits_phase : integer := 20;
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lo_nbits_freq : integer := 20;
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lo_nbits_phase : integer := 24;
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lo_nbits_freq : integer := 24;
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cic_nstages : integer := 5;
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cic_ratio : integer := 25;
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cic_scale_nbits : integer := 22;
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rfgen_nbits_phase : integer := 20;
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rfgen_nbits_freq : integer := 20
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rfgen_nbits_phase : integer := 32;
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rfgen_nbits_freq : integer := 32
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);
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END tb_ddc;
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@@ -108,7 +108,7 @@ ARCHITECTURE behavior OF tb_ddc IS
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END COMPONENT;
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--Constants
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constant fa : REAL := 100.0E6;
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constant fa : REAL := 2.0**27;
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constant frf1 : REAL := 33.99E6;
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constant frf2 : REAL := 2.1E6;
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constant frf3 : REAL := 19.01E6;
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@@ -352,6 +352,7 @@ BEGIN
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tb_param : PROCESS
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file RESULT_R: text open write_mode is "ratio.txt";
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file RESULT_N: text open write_mode is "nstages.txt";
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file FSAMPLE: text open write_mode is "fa.txt";
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variable L: line;
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BEGIN
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@@ -360,6 +361,7 @@ BEGIN
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wait until rising_edge(clk) and rst = '0';
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fprint(RESULT_R, L,"%s\n", natural'image(cic_ratio));
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fprint(RESULT_N, L,"%s\n", natural'image(cic_nstages));
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fprint(FSAMPLE, L,"%s\n", real'image(fa));
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wait;
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END PROCESS;
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