- uses only fir_pkg and filter_pkg for FIR

git-svn-id: http://moon:8086/svn/vhdl/trunk@193 cc03376c-175c-47c8-b038-4cd826a8556b

lib/filter/sim/tb_fir_iterative.fdo

@@ -6,9 +6,8 @@ vcom -explicit  -93 "../../../lib/fixed/fixed_util_pkg.vhd"
 vcom -explicit  -93 "../../../lib/PCK_FIO-2002.7/PCK_FIO_1993.vhd"
 vcom -explicit  -93 "../../../lib/PCK_FIO-2002.7/PCK_FIO_1993_BODY.vhd"
 vcom -explicit  -93 "../src/filter_pkg.vhd"
-vcom -explicit  -93 "../src/fir_stage_pkg.vhd"
+vcom -explicit  -93 "../src/fir_pkg.vhd"
 vcom -explicit  -93 "../src/fir_stage.vhd"
-vcom -explicit  -93 "../src/fir_iterative_pkg.vhd"
 vcom -explicit  -93 "../src/fir_iterative.vhd"
 vcom -explicit  -93 "../src/tb_fir_iterative.vhd"
 vsim -t 1ps   -lib work tb_fir_iterative

lib/filter/sim/tb_fir_iterative.wdo

@@ -53,8 +53,6 @@ add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_
 add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/ymem
 add wave -noupdate -divider {FIR Stage}
 add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/clk
-add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/inst_fir_stage/in_valid
-add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/inst_fir_stage/y_out_clr
 add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/inst_fir_stage/x_in
 add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/inst_fir_stage/h_in
 add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/inst_fir_stage/y_in
@@ -64,12 +62,72 @@ add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_
 add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/inst_fir_stage/prod
 add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/inst_fir_stage/x_out
 add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/inst_fir_stage/y_out
-add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/inst_fir_stage/valid
-add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/inst_fir_stage/p_valid
 add wave -noupdate -format Literal /tb_fir_iterative/uut_fir_iterative/s
-add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/inst_fir_stage/out_valid
+add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/srst
+add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/clk
+add wave -noupdate -format Literal /tb_fir_iterative/uut_fir_iterative/h_addr
+add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/ready
+add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/x_din
+add wave -noupdate -format Literal /tb_fir_iterative/uut_fir_iterative/s
+add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/xo
+add wave -noupdate -format Literal /tb_fir_iterative/coeffs
+add wave -noupdate -format Literal /tb_fir_iterative/uut_fir_iterative/xtap_cnt_w
+add wave -noupdate -format Literal /tb_fir_iterative/uut_fir_iterative/xtap_cnt_r
+add wave -noupdate -format Literal /tb_fir_iterative/uut_fir_iterative/htap_cnt
+add wave -noupdate -format Literal /tb_fir_iterative/xi
+add wave -noupdate -format Literal /tb_fir_iterative/yo
+add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/stage_en
+add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/fir_stage_clr
+add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/fir_stage_en
+add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/cnt_reset
+add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/x_valid
+add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/valid
+add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/y_valid
+add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/y_dout
+add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/new_round
+add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/x_stage
+add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/h_din
+add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/ymem
+add wave -noupdate -format Literal /tb_fir_iterative/uut_fir_iterative/xmem
+add wave -noupdate -divider {Xmem Dual}
+add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/srst
+add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/clk
+add wave -noupdate -format Literal /tb_fir_iterative/uut_fir_iterative/h_addr
+add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/ready
+add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/x_din
+add wave -noupdate -format Literal /tb_fir_iterative/uut_fir_iterative/s
+add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/xo
+add wave -noupdate -format Literal /tb_fir_iterative/coeffs
+add wave -noupdate -format Literal /tb_fir_iterative/uut_fir_iterative/xtap_cnt_w
+add wave -noupdate -format Literal /tb_fir_iterative/uut_fir_iterative/xtap_cnt_r
+add wave -noupdate -format Literal /tb_fir_iterative/uut_fir_iterative/htap_cnt
+add wave -noupdate -format Analog-Step -scale 10.0 /tb_fir_iterative/xi
+add wave -noupdate -format Analog-Step -scale 10.0 /tb_fir_iterative/yo
+add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/stage_en
+add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/valid
+add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/y_valid
+add wave -noupdate -format Logic /tb_fir_iterative/y_valid
+add wave -noupdate -format Analog-Step -radix decimal -scale 0.00061037000000000005 /tb_fir_iterative/uut_fir_iterative/y_dout
+add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/x_valid
+add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/new_round
+add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/x_stage
+add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/h_din
+add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/y_stage
+add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/ymem
+add wave -noupdate -divider {FIR Stage}
+add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/clk
+add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/inst_fir_stage/x_in
+add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/inst_fir_stage/h_in
+add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/inst_fir_stage/y_in
+add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/inst_fir_stage/xin
+add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/inst_fir_stage/hin
+add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/inst_fir_stage/yin
+add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/inst_fir_stage/prod
+add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/inst_fir_stage/x_out
+add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/inst_fir_stage/y_out
+add wave -noupdate -format Literal /tb_fir_iterative/uut_fir_iterative/s
 TreeUpdate [SetDefaultTree]
-WaveRestoreCursors {{Cursor 1} {1892287 ps} 0}
+WaveRestoreCursors {{Cursor 1} {5100000 ps} 0}
 configure wave -namecolwidth 140
 configure wave -valuecolwidth 100
 configure wave -justifyvalue left
@@ -83,4 +141,4 @@ configure wave -gridperiod 1
 configure wave -griddelta 40
 configure wave -timeline 0
 update
-WaveRestoreZoom {1750644 ps} {2771198 ps}
+WaveRestoreZoom {0 ps} {42 us}

lib/filter/sim/tb_fir_parallel.fdo

@@ -6,9 +6,8 @@ vcom -explicit  -93 "../../../lib/fixed/fixed_util_pkg.vhd"
 vcom -explicit  -93 "../../../lib/PCK_FIO-2002.7/PCK_FIO_1993.vhd"
 vcom -explicit  -93 "../../../lib/PCK_FIO-2002.7/PCK_FIO_1993_BODY.vhd"
 vcom -explicit  -93 "../src/filter_pkg.vhd"
-vcom -explicit  -93 "../src/fir_stage_pkg.vhd"
+vcom -explicit  -93 "../src/fir_pkg.vhd"
 vcom -explicit  -93 "../src/fir_stage.vhd"
-vcom -explicit  -93 "../src/fir_parallel_pkg.vhd"
 vcom -explicit  -93 "../src/fir_parallel.vhd"
 vcom -explicit  -93 "../src/tb_fir_parallel.vhd"
 vsim -t 1ps   -lib work tb_fir_parallel

lib/filter/sim/tb_fir_stage.fdo

@@ -6,7 +6,7 @@ vcom -explicit  -93 "../../../lib/fixed/fixed_util_pkg.vhd"
 vcom -explicit  -93 "../../../lib/PCK_FIO-2002.7/PCK_FIO_1993.vhd"
 vcom -explicit  -93 "../../../lib/PCK_FIO-2002.7/PCK_FIO_1993_BODY.vhd"
 vcom -explicit  -93 "../src/filter_pkg.vhd"
-vcom -explicit  -93 "../src/fir_stage_pkg.vhd"
+vcom -explicit  -93 "../src/fir_pkg.vhd"
 vcom -explicit  -93 "../src/fir_stage.vhd"
 vcom -explicit  -93 "../src/tb_fir_stage.vhd"
 vsim -t 1ps   -lib work tb_fir_stage

lib/filter/sim/tb_fir_stage_sys.fdo

@@ -6,7 +6,7 @@ vcom -explicit  -93 "../../../lib/fixed/fixed_util_pkg.vhd"
 vcom -explicit  -93 "../../../lib/PCK_FIO-2002.7/PCK_FIO_1993.vhd"
 vcom -explicit  -93 "../../../lib/PCK_FIO-2002.7/PCK_FIO_1993_BODY.vhd"
 vcom -explicit  -93 "../src/filter_pkg.vhd"
-vcom -explicit  -93 "../src/fir_stage_pkg.vhd"
+vcom -explicit  -93 "../src/fir_pkg.vhd"
 vcom -explicit  -93 "../src/fir_stage_sys.vhd"
 vcom -explicit  -93 "../src/tb_fir_stage_sys.vhd"
 vsim -t 1ps   -lib work tb_fir_stage_sys

lib/filter/src/fir_iterative.vhd

@@ -28,8 +28,7 @@ use ieee_proposed.fixed_pkg.all;
 
 library work;
 use work.fixed_util_pkg.all;
-use work.fir_stage_pkg.all;
+use work.fir_pkg.all;
-use work.fir_iterative_pkg.all;
 
 ---- Uncomment the following library declaration if instantiating
 ---- any Xilinx primitives in this code.

lib/filter/src/fir_parallel.vhd

@@ -29,8 +29,7 @@ use ieee_proposed.fixed_pkg.all;
 library work;
 use work.utils_pkg.all;
 use work.fixed_util_pkg.all;
-use work.fir_stage_pkg.all;
+use work.fir_pkg.all;
-use work.fir_parallel_pkg.all;
 
 ---- Uncomment the following library declaration if instantiating
 ---- any Xilinx primitives in this code.

lib/filter/src/fir_stage.vhd

@@ -29,7 +29,7 @@ use ieee_proposed.fixed_pkg.all;
 library work;
 use work.utils_pkg.all;
 use work.fixed_util_pkg.all;
-use work.fir_stage_pkg.all;
+use work.fir_pkg.all;
 
 ---- Uncomment the following library declaration if instantiating
 ---- any Xilinx primitives in this code.

lib/filter/src/fir_stage_sys.vhd

@@ -29,7 +29,7 @@ use ieee_proposed.fixed_pkg.all;
 library work;
 use work.utils_pkg.all;
 use work.fixed_util_pkg.all;
-use work.fir_stage_pkg.all;
+use work.fir_pkg.all;
 
 ---- Uncomment the following library declaration if instantiating
 ---- any Xilinx primitives in this code.

lib/filter/src/tb_fir_iterative.vhd

@@ -24,8 +24,7 @@ use ieee_proposed.fixed_pkg.all;
 library work;
 use work.fixed_util_pkg.all;
 use work.filter_pkg.all;
-use work.fir_stage_pkg.all;
+use work.fir_pkg.all;
-use work.fir_iterative_pkg.all;
 
 use work.PCK_FIO.all;
 
@@ -66,7 +65,7 @@ ARCHITECTURE behavior OF tb_fir_iterative IS
 		srst			: in std_logic;
 		clk				: in std_logic;
 		h_din			: in sfixed;
-		h_addr_out		: out unsigned(taps_nbits(ntaps, fir_mode)-1 downto 0);
+		h_addr_out		: out natural;
 		ready			: out std_logic;
 		x_valid			: in std_logic;
 		x_din			: in sfixed;
@@ -141,7 +140,7 @@ ARCHITECTURE behavior OF tb_fir_iterative IS
 	
 	signal y_cnt : integer ;
 	SIGNAL xi, yo : real := 0.0;
-	SIGNAL h_addr : unsigned(taps_nbits(ntaps, fir_mode)-1 downto 0);
+	SIGNAL h_addr : natural;
 	
 	-- file I/O
 	subtype sample_t is integer range -32768 to 32767;
@@ -221,7 +220,7 @@ BEGIN
 	process(srst, clk, y_valid)
 	begin
 		if rising_edge(clk) then
-			h_din <= to_sfixed(coeffs(to_integer(h_addr)), h_din);
+			h_din <= to_sfixed(coeffs(h_addr), h_din);
 			if srst = '1' then
 				y_cnt <= 0;
 				

lib/filter/src/tb_fir_parallel.vhd

@@ -23,9 +23,8 @@ use ieee_proposed.fixed_pkg.all;
 
 library work;
 use work.fixed_util_pkg.all;
-use work.fir_stage_pkg.all;
-use work.fir_parallel_pkg.all;
 use work.filter_pkg.all;
+use work.fir_pkg.all;
 
 use work.PCK_FIO.all;
 

lib/filter/src/tb_fir_stage.vhd

@@ -23,7 +23,7 @@ use ieee_proposed.fixed_pkg.all;
 
 library work;
 use work.fixed_util_pkg.all;
-use work.fir_stage_pkg.all;
+use work.fir_pkg.all;
 use work.filter_pkg.all;
 
 use work.PCK_FIO.all;

lib/filter/src/tb_fir_stage_sys.vhd

@@ -23,7 +23,7 @@ use ieee_proposed.fixed_pkg.all;
 
 library work;
 use work.fixed_util_pkg.all;
-use work.fir_stage_pkg.all;
+use work.fir_pkg.all;
 use work.filter_pkg.all;
 
 use work.PCK_FIO.all;