- uses only fir_pkg and filter_pkg for FIR

git-svn-id: http://moon:8086/svn/vhdl/trunk@193 cc03376c-175c-47c8-b038-4cd826a8556b

lib/filter/src/fir_iterative.vhd

@@ -28,8 +28,7 @@ use ieee_proposed.fixed_pkg.all;
 
 library work;
 use work.fixed_util_pkg.all;
-use work.fir_stage_pkg.all;
-use work.fir_iterative_pkg.all;
+use work.fir_pkg.all;
 
 ---- Uncomment the following library declaration if instantiating
 ---- any Xilinx primitives in this code.

lib/filter/src/fir_parallel.vhd

@@ -29,8 +29,7 @@ use ieee_proposed.fixed_pkg.all;
 library work;
 use work.utils_pkg.all;
 use work.fixed_util_pkg.all;
-use work.fir_stage_pkg.all;
-use work.fir_parallel_pkg.all;
+use work.fir_pkg.all;
 
 ---- Uncomment the following library declaration if instantiating
 ---- any Xilinx primitives in this code.

lib/filter/src/fir_stage.vhd

@@ -29,7 +29,7 @@ use ieee_proposed.fixed_pkg.all;
 library work;
 use work.utils_pkg.all;
 use work.fixed_util_pkg.all;
-use work.fir_stage_pkg.all;
+use work.fir_pkg.all;
 
 ---- Uncomment the following library declaration if instantiating
 ---- any Xilinx primitives in this code.

lib/filter/src/fir_stage_sys.vhd

@@ -29,7 +29,7 @@ use ieee_proposed.fixed_pkg.all;
 library work;
 use work.utils_pkg.all;
 use work.fixed_util_pkg.all;
-use work.fir_stage_pkg.all;
+use work.fir_pkg.all;
 
 ---- Uncomment the following library declaration if instantiating
 ---- any Xilinx primitives in this code.

lib/filter/src/tb_fir_iterative.vhd

@@ -24,8 +24,7 @@ use ieee_proposed.fixed_pkg.all;
 library work;
 use work.fixed_util_pkg.all;
 use work.filter_pkg.all;
-use work.fir_stage_pkg.all;
-use work.fir_iterative_pkg.all;
+use work.fir_pkg.all;
 
 use work.PCK_FIO.all;
 
@@ -66,7 +65,7 @@ ARCHITECTURE behavior OF tb_fir_iterative IS
 		srst			: in std_logic;
 		clk				: in std_logic;
 		h_din			: in sfixed;
-		h_addr_out		: out unsigned(taps_nbits(ntaps, fir_mode)-1 downto 0);
+		h_addr_out		: out natural;
 		ready			: out std_logic;
 		x_valid			: in std_logic;
 		x_din			: in sfixed;
@@ -141,7 +140,7 @@ ARCHITECTURE behavior OF tb_fir_iterative IS
 	
 	signal y_cnt : integer ;
 	SIGNAL xi, yo : real := 0.0;
-	SIGNAL h_addr : unsigned(taps_nbits(ntaps, fir_mode)-1 downto 0);
+	SIGNAL h_addr : natural;
 	
 	-- file I/O
 	subtype sample_t is integer range -32768 to 32767;
@@ -221,7 +220,7 @@ BEGIN
 	process(srst, clk, y_valid)
 	begin
 		if rising_edge(clk) then
-			h_din <= to_sfixed(coeffs(to_integer(h_addr)), h_din);
+			h_din <= to_sfixed(coeffs(h_addr), h_din);
 			if srst = '1' then
 				y_cnt <= 0;
 				

lib/filter/src/tb_fir_parallel.vhd

@@ -23,9 +23,8 @@ use ieee_proposed.fixed_pkg.all;
 
 library work;
 use work.fixed_util_pkg.all;
-use work.fir_stage_pkg.all;
-use work.fir_parallel_pkg.all;
 use work.filter_pkg.all;
+use work.fir_pkg.all;
 
 use work.PCK_FIO.all;
 

lib/filter/src/tb_fir_stage.vhd

@@ -23,7 +23,7 @@ use ieee_proposed.fixed_pkg.all;
 
 library work;
 use work.fixed_util_pkg.all;
-use work.fir_stage_pkg.all;
+use work.fir_pkg.all;
 use work.filter_pkg.all;
 
 use work.PCK_FIO.all;

lib/filter/src/tb_fir_stage_sys.vhd

@@ -23,7 +23,7 @@ use ieee_proposed.fixed_pkg.all;
 
 library work;
 use work.fixed_util_pkg.all;
-use work.fir_stage_pkg.all;
+use work.fir_pkg.all;
 use work.filter_pkg.all;
 
 use work.PCK_FIO.all;