- refactored

git-svn-id: http://moon:8086/svn/vhdl/trunk@1483 cc03376c-175c-47c8-b038-4cd826a8556b
2021-03-23 11:41:42 +00:00
parent a1df4a5323
commit d249d20b50
19 changed files with 0 additions and 0 deletions
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+-------------------------------------------------------------------------
+-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
+-- This file: cpu_embedded using cpu_core and rom
+--
+-- Copyright (C) 2007 J. Ahrensfeld
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
+--
+-- For questions and ideas, please contact the author at jens@jayfield.org
+--
+--------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.numeric_std.ALL;
+
+LIBRARY WORK;
+USE WORK.uart_types.all;
+
+entity tb_uart is
+end;
+
+architecture behave of tb_uart is
+
+	-- Number of user data words for simulation
+	constant CLK_PERIOD		: time := 10 ns;
+	constant BAUD_DIV		: natural := 2;
+
+	-- Common
+	signal rst				: std_logic := '1';  
+	signal clk				: std_logic := '1';  
+	signal ctrl				: ctrl_t;  
+	signal status			: status_t;  
+	
+	-- TX
+	signal tx_we			: std_logic := '0';  
+	signal tx_ser			: std_logic;  
+	signal tx_din			: unsigned(7 downto 0) := (others => '0');
+
+	-- RX
+	signal rx_re			: std_logic := '0';  
+	signal rx_ser			: std_logic := '1';  
+	signal rx_dout			: unsigned(7 downto 0);
+	
+	-- Others
+	signal data_rx			: unsigned(7 downto 0);
+	signal data_tx			: unsigned(7 downto 0);
+	signal count_rx			: natural;
+
+begin
+
+	rx_ser			<= tx_ser;
+	ctrl.baudrate	<= to_unsigned(BAUD_DIV-1, ctrl.baudrate'length);
+	
+dut : entity work.uart
+	PORT MAP
+	(
+		rst					=> rst,
+		clk					=> clk,
+		we					=> tx_we,
+		re					=> rx_re,
+		din					=> tx_din,
+		dout				=> rx_dout,
+		ser_tx				=> tx_ser,
+		ser_rx				=> rx_ser,
+		ctrl				=> ctrl,
+		status				=> status
+	);
+
+CLK_GEN: process
+	begin
+		wait for CLK_PERIOD/2;
+		clk <= not clk;
+	end process;
+
+PROC_DATAREG_RX:
+	process (clk)
+	begin
+		if rising_edge(clk) then
+			if rst = '1' then
+				count_rx <= 0;
+			elsif status.rx_present = '1' and rx_re = '1' then
+--				assert rx_dout = count_rx report "Data mismatch" severity failure;
+				data_rx 	<= rx_dout;
+				count_rx	<= count_rx + 1;
+			end if;
+		end if;
+	end process;
+
+PROC_RX_RE: process
+	begin
+		wait for 10 us;
+		rx_re	<= status.rx_present;
+	end process;
+
+PROC_DATAREG_TX: process
+	begin
+		wait until rising_edge(clk) and tx_we = '1';
+		data_tx <= tx_din;
+	end process;
+
+------------------------------------------------------------------------------------------
+
+STIMULUS: process
+
+
+	begin
+
+		wait for 3*CLK_PERIOD;
+		rst <= '0';
+		wait for 3*CLK_PERIOD;
+		wait until rising_edge(clk);
+		
+		for i in 0 to 255 loop
+			wait until rising_edge(clk);
+			tx_din <= to_unsigned(i, 8);
+			tx_we <= '1';
+			wait until rising_edge(clk) and status.tx_full = '0';
+			tx_we <= '0';
+		end loop;
+		wait; 
+	
+	end process;
+	
+end architecture behave;