- refactored

git-svn-id: http://moon:8086/svn/vhdl/trunk@1483 cc03376c-175c-47c8-b038-4cd826a8556b
2021-03-23 11:41:42 +00:00
parent a1df4a5323
commit d249d20b50
19 changed files with 0 additions and 0 deletions
@@ -0,0 +1,69 @@
+LIBRARY IEEE;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.NUMERIC_STD.ALL;
+
+LIBRARY WORK;
+USE WORK.uart_types.all;
+
+use std.textio.all; --  Imports the standard textio package.
+
+------------------------------------------------------------------------------------
+ENTITY uart IS
+	Generic 
+	(
+		fifo_depth_bits	: integer := 4
+	);
+	Port
+	(
+		clk			: in  STD_LOGIC;
+		rst			: in  STD_LOGIC;
+		we			: in  STD_LOGIC;
+		re			: in  STD_LOGIC;
+		din			: in  unsigned(7 downto 0);
+		dout		: out unsigned(7 downto 0);
+		ser_rx		: in std_logic;
+		ser_tx		: out std_logic;
+		ctrl		: in ctrl_t;
+		status		: out status_t
+	);
+END uart;
+
+ARCHITECTURE simulation OF uart IS
+begin
+
+-- RX
+dout			        <= X"00";
+status.rx_present		<= '0';
+
+-- TX
+ser_tx 					<= '1';
+status.tx_complete		<= '1';
+status.tx_empty			<= '1';
+status.tx_full			<= '0';
+
+proc_tx: 
+	process(clk)
+	file output:	      text open write_mode is "STD_OUTPUT"; 
+	variable L : line; 
+	begin
+		if rising_edge(clk) then
+			if we = '1' then
+				if din /= X"0D" then
+					write(L, character'val(to_integer(din)));
+				end if;	
+				if din = X"0A" then
+					writeline(output, L);
+				end if;
+			end if;	
+		end if;	
+	end process;
+
+end simulation;
+
+------------------------------------------------------------------------------------
+--
+-- END OF FILE UART_RX.VHD
+--
+------------------------------------------------------------------------------------
+
+