- refactored
git-svn-id: http://moon:8086/svn/vhdl/trunk@1483 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
@@ -0,0 +1,184 @@
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-- UART Receiver
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--
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-- Version : 1.00
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-- Version Date : 15 December 2016
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--
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------------------------------------------------------------------------------------
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--
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-- Library declarations
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--
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-- The Unisim Library is used to define Xilinx primitives. It is also used during
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-- simulation. The source can be viewed at %XILINX%\vhdl\src\unisims\unisim_VCOMP.vhd
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--
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.numeric_std.ALL;
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--
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------------------------------------------------------------------------------------
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--
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-- Main Entity
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--
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entity juart_rx is
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Port
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(
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rst : in std_logic;
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clk : in std_logic;
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ser_in : in std_logic;
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dout : out unsigned(7 downto 0);
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dout_vld : out std_logic;
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en_16_x_baud : in std_logic
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);
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end juart_rx;
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--
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------------------------------------------------------------------------------------
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--
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-- Start of Main Architecture
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--
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architecture behavior of juart_rx is
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--
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------------------------------------------------------------------------------------
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--
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------------------------------------------------------------------------------------
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--
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-- Signals used
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--
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------------------------------------------------------------------------------------
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--
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constant OVERSAMPLING : natural := 16;
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subtype bit_count_t is natural range 0 to OVERSAMPLING-1;
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signal bit_count_rst : std_logic;
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signal bit_count : bit_count_t;
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signal data_valid : std_logic;
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signal shiftreg_en : std_logic;
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signal shiftreg : unsigned (7 downto 0);
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signal sample_count_rst : std_logic;
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signal sample_count : natural range 0 to OVERSAMPLING-1;
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signal bit_sample : std_logic;
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type state_t is (idle, wait_start, start, shift, stop);
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signal state : state_t;
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signal state_next : state_t;
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--
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--
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begin
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data_out_reg:
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process(clk)
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begin
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if rising_edge(clk) then
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dout_vld <= '0';
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if data_valid = '1' then
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dout <= shiftreg;
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dout_vld <= '1';
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end if;
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end if;
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end process;
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proc_state_next:
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process(clk)
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begin
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if rising_edge(clk) then
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if rst = '1' then
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state <= idle;
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else
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state <= state_next;
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end if;
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end if;
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end process;
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statemachine:
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process(state, bit_count, bit_sample, ser_in)
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begin
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state_next <= state;
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sample_count_rst <= '0';
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bit_count_rst <= '0';
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shiftreg_en <= '0';
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data_valid <= '0';
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case state is
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when idle =>
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if ser_in = '1' then
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state_next <= wait_start;
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end if;
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when wait_start =>
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sample_count_rst <= '1';
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if ser_in = '0' then
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state_next <= start;
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end if;
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when start =>
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bit_count_rst <= '1';
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if bit_sample = '1' then
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state_next <= shift;
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end if;
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when shift =>
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shiftreg_en <= '1';
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if bit_count = 8 then
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state_next <= stop;
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end if;
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when stop =>
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if bit_sample = '1' then
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state_next <= idle;
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data_valid <= '1';
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end if;
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when others =>
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state_next <= idle;
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end case;
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end process;
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shift_register:
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process(clk)
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begin
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if rising_edge(clk) then
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if rst = '1' then
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shiftreg <= (others => '0');
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elsif shiftreg_en = '1' and bit_sample = '1' then
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shiftreg <= ser_in & shiftreg(shiftreg'left downto 1);
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end if;
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end if;
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end process;
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sample_counter:
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process(clk)
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begin
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if rising_edge(clk) then
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bit_sample <= '0';
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if sample_count_rst = '1' then
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sample_count <= 0;
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elsif en_16_x_baud = '1' then
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if sample_count /= OVERSAMPLING-1 then
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sample_count <= sample_count + 1;
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else
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sample_count <= 0;
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end if;
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if sample_count = OVERSAMPLING/2-1 then
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bit_sample <= '1';
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end if;
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end if;
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end if;
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end process;
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bit_counter:
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process(clk)
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begin
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if rising_edge(clk) then
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if bit_count_rst = '1' then
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bit_count <= 0;
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elsif bit_count /= bit_count_t'high and bit_sample = '1' then
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bit_count <= bit_count + 1;
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end if;
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end if;
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end process;
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end behavior;
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------------------------------------------------------------------------------------
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--
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-- END OF FILE
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--
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------------------------------------------------------------------------------------
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@@ -0,0 +1,126 @@
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-- UART Transmitter
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--
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-- Version : 1.00
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-- Version Date : 15 December 2016
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--
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------------------------------------------------------------------------------------
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--
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.numeric_std.ALL;
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--
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------------------------------------------------------------------------------------
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--
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-- Main Entity
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--
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entity juart_tx is
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Port
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(
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rst : in std_logic;
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clk : in std_logic;
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we : in std_logic;
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din : in unsigned(7 downto 0);
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en_16_x_baud : in std_logic;
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Tx_complete : out std_logic;
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ser_out : out std_logic
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);
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end juart_tx;
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--
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------------------------------------------------------------------------------------
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--
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-- Start of Main Architecture
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--
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architecture behavior of juart_tx is
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--
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------------------------------------------------------------------------------------
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--
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------------------------------------------------------------------------------------
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--
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-- Signals used
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--
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------------------------------------------------------------------------------------
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--
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signal dinreg : unsigned (7 downto 0);
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signal shiftreg : unsigned (9 downto 0);
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signal busy : std_logic;
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signal start : std_logic;
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signal shift_enable : std_logic;
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signal shift_enable_count : unsigned (3 downto 0);
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signal bit_count : unsigned (3 downto 0);
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--
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--
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begin
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ser_out <= shiftreg(0);
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Tx_complete <= not busy;
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shift_enable_counter:
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process(clk)
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begin
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if rising_edge(clk) then
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shift_enable <= '0';
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if rst = '1' then
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shift_enable_count <= (others => '1');
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elsif en_16_x_baud = '1' then
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if shift_enable_count = 0 then
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shift_enable <= '1';
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shift_enable_count <= (others => '1');
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else
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shift_enable_count <= shift_enable_count - 1;
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end if;
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end if;
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end if;
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end process;
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bit_counter:
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process(clk)
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begin
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if rising_edge(clk) then
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if start = '1' then
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bit_count <= to_unsigned(shiftreg'length-1, bit_count'length);
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elsif shift_enable = '1' then
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if not (bit_count = 0) then
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bit_count <= bit_count - 1;
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end if;
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end if;
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end if;
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end process;
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transmit:
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process(clk)
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begin
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if rising_edge(clk) then
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if rst = '1' then
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shiftreg <= (others => '1');
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busy <= '0';
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start <= '0';
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elsif busy = '0' then
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if we = '1' then
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busy <= '1';
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start <= '1';
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dinreg <= din;
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end if;
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elsif shift_enable = '1' then
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if start = '1' then
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start <= '0';
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shiftreg <= '1' & dinreg & '0';
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elsif bit_count /= 0 then
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shiftreg <= '1' & shiftreg(shiftreg'left downto 1);
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if bit_count = 1 then
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busy <= '0';
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end if;
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end if;
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end if;
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end if;
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end process;
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end behavior;
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------------------------------------------------------------------------------------
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--
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-- END OF FILE
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--
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------------------------------------------------------------------------------------
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@@ -0,0 +1,123 @@
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-------------------------------------------------------------------------
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-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
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-- This file: cpu_embedded using cpu_core and rom
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--
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-- Copyright (C) 2007 J. Ahrensfeld
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||||
--
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-- This program is free software: you can redistribute it and/or modify
|
||||
-- it under the terms of the GNU General Public License as published by
|
||||
-- the Free Software Foundation, either version 3 of the License, or
|
||||
-- (at your option) any later version.
|
||||
--
|
||||
-- This program is distributed in the hope that it will be useful,
|
||||
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
-- GNU General Public License for more details.
|
||||
--
|
||||
-- You should have received a copy of the GNU General Public License
|
||||
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
--
|
||||
-- For questions and ideas, please contact the author at jens@jayfield.org
|
||||
--
|
||||
--------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.numeric_std.ALL;
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entity tb_juart_rx is
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end;
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architecture behave of tb_juart_rx is
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-- Number of user data words for simulation
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constant CLK_PERIOD : time := 10 ns;
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constant BAUD_DIV : natural := 2;
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signal rst : std_logic := '1';
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signal clk : std_logic := '1';
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signal en_16_x_baud : std_logic := '1';
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signal ser_in : std_logic := '1';
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signal dout_vld : std_logic;
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signal dout : unsigned(7 downto 0);
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signal serial_word : unsigned(7 downto 0) := X"AA";
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signal baud_count : unsigned(15 downto 0);
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signal baud_reg : unsigned(15 downto 0) := to_unsigned(BAUD_DIV-1, baud_count'length);
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signal data_reg : unsigned(7 downto 0);
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begin
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dut : entity work.juart_rx
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PORT MAP
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(
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rst => rst,
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clk => clk,
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en_16_x_baud => en_16_x_baud,
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dout_vld => dout_vld,
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dout => dout,
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ser_in => ser_in
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);
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CLK_GEN: process
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begin
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wait for CLK_PERIOD/2;
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clk <= not clk;
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end process;
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PROC_DATAREG: process
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begin
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wait until rising_edge(clk) and dout_vld = '1';
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data_reg <= dout;
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end process;
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baud_timer:
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process(clk)
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begin
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if rising_edge(clk) then
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en_16_x_baud <= '0';
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if rst = '1' then
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baud_count <= (others => '0');
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elsif baud_count = baud_reg then
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baud_count <= (others => '0');
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en_16_x_baud <= '1';
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else
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baud_count <= baud_count + 1;
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end if;
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end if;
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end process;
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------------------------------------------------------------------------------------------
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STIMULUS: process
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begin
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wait for 3*CLK_PERIOD;
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rst <= '0';
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serial_word <= X"AA";
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wait for 16*baud_div*CLK_PERIOD;
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ser_in <= '0';
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wait for 16*baud_div*CLK_PERIOD;
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for i in serial_word'length-1 downto 0 loop
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ser_in <= serial_word(i);
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wait for 16*baud_div*CLK_PERIOD;
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end loop;
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ser_in <= '1';
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wait for 16*baud_div*CLK_PERIOD;
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serial_word <= X"55";
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ser_in <= '0';
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wait for 16*baud_div*CLK_PERIOD;
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for i in serial_word'length-1 downto 0 loop
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ser_in <= serial_word(i);
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wait for 16*baud_div*CLK_PERIOD;
|
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end loop;
|
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ser_in <= '1';
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wait;
|
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|
||||
end process;
|
||||
|
||||
end architecture behave;
|
||||
@@ -0,0 +1,115 @@
|
||||
-------------------------------------------------------------------------
|
||||
-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
|
||||
-- This file: cpu_embedded using cpu_core and rom
|
||||
--
|
||||
-- Copyright (C) 2007 J. Ahrensfeld
|
||||
--
|
||||
-- This program is free software: you can redistribute it and/or modify
|
||||
-- it under the terms of the GNU General Public License as published by
|
||||
-- the Free Software Foundation, either version 3 of the License, or
|
||||
-- (at your option) any later version.
|
||||
--
|
||||
-- This program is distributed in the hope that it will be useful,
|
||||
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
-- GNU General Public License for more details.
|
||||
--
|
||||
-- You should have received a copy of the GNU General Public License
|
||||
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
--
|
||||
-- For questions and ideas, please contact the author at jens@jayfield.org
|
||||
--
|
||||
--------------------------------------------------------------------------
|
||||
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
use IEEE.numeric_std.ALL;
|
||||
|
||||
entity tb_juart_tx is
|
||||
end;
|
||||
|
||||
architecture behave of tb_juart_tx is
|
||||
|
||||
-- Number of user data words for simulation
|
||||
constant CLK_PERIOD : time := 10 ns;
|
||||
constant BAUD_DIV : natural := 2;
|
||||
|
||||
signal rst : std_logic := '1';
|
||||
signal clk : std_logic := '1';
|
||||
signal en_16_x_baud : std_logic := '1';
|
||||
signal we : std_logic := '0';
|
||||
signal ser_out : std_logic;
|
||||
signal Tx_complete : std_logic;
|
||||
signal din : unsigned(7 downto 0) := (others => '0');
|
||||
|
||||
signal baud_count : unsigned(15 downto 0);
|
||||
signal baud_reg : unsigned(15 downto 0) := to_unsigned(BAUD_DIV-1, baud_count'length);
|
||||
begin
|
||||
|
||||
dut : entity work.juart_tx
|
||||
PORT MAP
|
||||
(
|
||||
rst => rst,
|
||||
clk => clk,
|
||||
we => we,
|
||||
din => din,
|
||||
en_16_x_baud => en_16_x_baud,
|
||||
Tx_complete => Tx_complete,
|
||||
ser_out => ser_out
|
||||
);
|
||||
|
||||
|
||||
CLK_GEN: process
|
||||
begin
|
||||
wait for CLK_PERIOD/2;
|
||||
clk <= not clk;
|
||||
end process;
|
||||
|
||||
baud_timer:
|
||||
process(clk)
|
||||
begin
|
||||
if rising_edge(clk) then
|
||||
en_16_x_baud <= '0';
|
||||
if rst = '1' then
|
||||
baud_count <= (others => '0');
|
||||
elsif baud_count = baud_reg then
|
||||
baud_count <= (others => '0');
|
||||
en_16_x_baud <= '1';
|
||||
else
|
||||
baud_count <= baud_count + 1;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
------------------------------------------------------------------------------------------
|
||||
|
||||
STIMULUS: process
|
||||
|
||||
|
||||
begin
|
||||
|
||||
wait for 3*CLK_PERIOD;
|
||||
rst <= '0';
|
||||
wait for 3*CLK_PERIOD;
|
||||
wait until rising_edge(clk);
|
||||
din <= X"A5";
|
||||
wait until rising_edge(clk) and Tx_complete = '1';
|
||||
we <= '1';
|
||||
wait until rising_edge(clk) and Tx_complete = '0';
|
||||
we <= '0';
|
||||
wait until rising_edge(clk) and Tx_complete = '1';
|
||||
din <= X"AA";
|
||||
wait until rising_edge(clk) and Tx_complete = '1';
|
||||
we <= '1';
|
||||
wait until rising_edge(clk) and Tx_complete = '0';
|
||||
we <= '0';
|
||||
din <= X"55";
|
||||
wait until rising_edge(clk) and Tx_complete = '1';
|
||||
we <= '1';
|
||||
wait until rising_edge(clk) and Tx_complete = '0';
|
||||
we <= '0';
|
||||
wait;
|
||||
|
||||
end process;
|
||||
|
||||
end architecture behave;
|
||||
@@ -0,0 +1,144 @@
|
||||
-------------------------------------------------------------------------
|
||||
-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
|
||||
-- This file: cpu_embedded using cpu_core and rom
|
||||
--
|
||||
-- Copyright (C) 2007 J. Ahrensfeld
|
||||
--
|
||||
-- This program is free software: you can redistribute it and/or modify
|
||||
-- it under the terms of the GNU General Public License as published by
|
||||
-- the Free Software Foundation, either version 3 of the License, or
|
||||
-- (at your option) any later version.
|
||||
--
|
||||
-- This program is distributed in the hope that it will be useful,
|
||||
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
-- GNU General Public License for more details.
|
||||
--
|
||||
-- You should have received a copy of the GNU General Public License
|
||||
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
--
|
||||
-- For questions and ideas, please contact the author at jens@jayfield.org
|
||||
--
|
||||
--------------------------------------------------------------------------
|
||||
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
use IEEE.numeric_std.ALL;
|
||||
|
||||
entity tb_juart_tx_rx is
|
||||
end;
|
||||
|
||||
architecture behave of tb_juart_tx_rx is
|
||||
|
||||
-- Number of user data words for simulation
|
||||
constant CLK_PERIOD : time := 10 ns;
|
||||
constant BAUD_DIV : natural := 2;
|
||||
|
||||
-- Common
|
||||
signal rst : std_logic := '1';
|
||||
signal clk : std_logic := '1';
|
||||
signal en_16_x_baud : std_logic := '1';
|
||||
|
||||
-- TX
|
||||
signal tx_we : std_logic := '0';
|
||||
signal ser_out : std_logic;
|
||||
signal Tx_complete : std_logic;
|
||||
signal tx_din : unsigned(7 downto 0) := (others => '0');
|
||||
|
||||
-- RX
|
||||
signal ser_in : std_logic := '1';
|
||||
signal rx_dout_vld : std_logic;
|
||||
signal rx_dout : unsigned(7 downto 0);
|
||||
|
||||
-- Others
|
||||
signal baud_count : unsigned(15 downto 0);
|
||||
signal baud_reg : unsigned(15 downto 0) := to_unsigned(BAUD_DIV-1, baud_count'length);
|
||||
signal data_rx : unsigned(7 downto 0);
|
||||
signal data_tx : unsigned(7 downto 0);
|
||||
|
||||
begin
|
||||
|
||||
ser_in <= ser_out;
|
||||
|
||||
inst_juart_tx : entity work.juart_tx
|
||||
PORT MAP
|
||||
(
|
||||
rst => rst,
|
||||
clk => clk,
|
||||
we => tx_we,
|
||||
din => tx_din,
|
||||
en_16_x_baud => en_16_x_baud,
|
||||
Tx_complete => Tx_complete,
|
||||
ser_out => ser_out
|
||||
);
|
||||
|
||||
inst_juart_rx : entity work.juart_rx
|
||||
PORT MAP
|
||||
(
|
||||
rst => rst,
|
||||
clk => clk,
|
||||
en_16_x_baud => en_16_x_baud,
|
||||
dout_vld => rx_dout_vld,
|
||||
dout => rx_dout,
|
||||
ser_in => ser_in
|
||||
);
|
||||
|
||||
CLK_GEN: process
|
||||
begin
|
||||
wait for CLK_PERIOD/2;
|
||||
clk <= not clk;
|
||||
end process;
|
||||
|
||||
PROC_DATAREG_RX: process
|
||||
begin
|
||||
wait until rising_edge(clk) and rx_dout_vld = '1';
|
||||
data_rx <= rx_dout;
|
||||
assert rx_dout = data_tx report "Data mismatch" severity failure;
|
||||
end process;
|
||||
|
||||
PROC_DATAREG_TX: process
|
||||
begin
|
||||
wait until rising_edge(clk) and tx_we = '1';
|
||||
data_tx <= tx_din;
|
||||
end process;
|
||||
|
||||
baud_timer:
|
||||
process(clk)
|
||||
begin
|
||||
if rising_edge(clk) then
|
||||
en_16_x_baud <= '0';
|
||||
if rst = '1' then
|
||||
baud_count <= (others => '0');
|
||||
elsif baud_count = baud_reg then
|
||||
baud_count <= (others => '0');
|
||||
en_16_x_baud <= '1';
|
||||
else
|
||||
baud_count <= baud_count + 1;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
------------------------------------------------------------------------------------------
|
||||
|
||||
STIMULUS: process
|
||||
|
||||
|
||||
begin
|
||||
|
||||
wait for 3*CLK_PERIOD;
|
||||
rst <= '0';
|
||||
wait for 3*CLK_PERIOD;
|
||||
wait until rising_edge(clk);
|
||||
|
||||
for i in 0 to 255 loop
|
||||
wait until rising_edge(clk) and Tx_complete = '1';
|
||||
tx_din <= to_unsigned(i, 8);
|
||||
tx_we <= '1';
|
||||
wait until rising_edge(clk) and Tx_complete = '0';
|
||||
tx_we <= '0';
|
||||
end loop;
|
||||
wait;
|
||||
|
||||
end process;
|
||||
|
||||
end architecture behave;
|
||||
@@ -0,0 +1,112 @@
|
||||
LIBRARY IEEE;
|
||||
USE IEEE.STD_LOGIC_1164.ALL;
|
||||
USE IEEE.NUMERIC_STD.ALL;
|
||||
|
||||
LIBRARY WORK;
|
||||
USE WORK.uart_types.all;
|
||||
|
||||
------------------------------------------------------------------------------------
|
||||
ENTITY uart IS
|
||||
Generic
|
||||
(
|
||||
fifo_depth_bits : integer := 4
|
||||
);
|
||||
Port
|
||||
(
|
||||
clk : in STD_LOGIC;
|
||||
rst : in STD_LOGIC;
|
||||
we : in STD_LOGIC;
|
||||
re : in STD_LOGIC;
|
||||
din : in unsigned(7 downto 0);
|
||||
dout : out unsigned(7 downto 0);
|
||||
ser_rx : in std_logic;
|
||||
ser_tx : out std_logic;
|
||||
ctrl : in ctrl_t;
|
||||
status : out status_t
|
||||
);
|
||||
END uart;
|
||||
|
||||
ARCHITECTURE rtl OF uart IS
|
||||
|
||||
signal baud_count : unsigned(15 downto 0);
|
||||
signal en_16_x_baud : std_logic;
|
||||
|
||||
signal rx_dout_vld : std_logic;
|
||||
signal rx_full : std_logic;
|
||||
signal rx_half_full : std_logic;
|
||||
|
||||
signal tx_complete : std_logic;
|
||||
signal tx_empty : std_logic;
|
||||
signal tx_full : std_logic;
|
||||
signal tx_half_full : std_logic;
|
||||
|
||||
begin
|
||||
|
||||
baud_timer:
|
||||
process(clk)
|
||||
begin
|
||||
if rising_edge(clk) then
|
||||
en_16_x_baud <= '0';
|
||||
if rst = '1' then
|
||||
baud_count <= (others => '0');
|
||||
elsif baud_count = ctrl.baudrate then
|
||||
baud_count <= (others => '0');
|
||||
en_16_x_baud <= '1';
|
||||
else
|
||||
baud_count <= baud_count + 1;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
inst_uart_tx : entity work.uart_tx
|
||||
GENERIC MAP
|
||||
(
|
||||
fifo_depth_bits => fifo_depth_bits
|
||||
)
|
||||
PORT MAP
|
||||
(
|
||||
rst => rst,
|
||||
clk => clk,
|
||||
we => we,
|
||||
din => din,
|
||||
en_16_x_baud => en_16_x_baud,
|
||||
full => tx_full,
|
||||
half_full => tx_half_full,
|
||||
tx_complete => tx_complete,
|
||||
tx_empty => tx_empty,
|
||||
ser_out => ser_tx
|
||||
);
|
||||
|
||||
inst_uart_rx : entity work.uart_rx
|
||||
GENERIC MAP
|
||||
(
|
||||
fifo_depth_bits => fifo_depth_bits
|
||||
)
|
||||
PORT MAP
|
||||
(
|
||||
rst => rst,
|
||||
clk => clk,
|
||||
en_16_x_baud => en_16_x_baud,
|
||||
dout_vld => rx_dout_vld,
|
||||
dout => dout,
|
||||
re => re,
|
||||
full => rx_full,
|
||||
half_full => rx_half_full,
|
||||
ser_in => ser_rx
|
||||
);
|
||||
|
||||
-- Status
|
||||
status.rx_present <= rx_dout_vld;
|
||||
status.tx_complete <= tx_complete;
|
||||
status.tx_empty <= tx_empty;
|
||||
status.tx_full <= tx_full;
|
||||
|
||||
end rtl;
|
||||
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
-- END OF FILE UART_RX.VHD
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
|
||||
|
||||
@@ -0,0 +1,133 @@
|
||||
-- UART Receiver with integral 16 byte FIFO buffer
|
||||
--
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
use IEEE.numeric_std.ALL;
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
-- Main Entity for UART_TX
|
||||
--
|
||||
entity uart_rx is
|
||||
Generic
|
||||
(
|
||||
fifo_depth_bits : integer := 4
|
||||
);
|
||||
Port
|
||||
(
|
||||
rst : in std_logic;
|
||||
clk : in std_logic;
|
||||
re : in std_logic;
|
||||
full : out std_logic;
|
||||
half_full : out std_logic;
|
||||
ser_in : in std_logic;
|
||||
dout_vld : out std_logic;
|
||||
dout : out unsigned(7 downto 0);
|
||||
en_16_x_baud : in std_logic
|
||||
);
|
||||
end uart_rx;
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
-- Start of Main Architecture for UART_TX
|
||||
--
|
||||
architecture rtl of uart_rx is
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
-- Components used in UART_TX and defined in subsequent entities.
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
-- Constant (K) Compact UART Transmitter
|
||||
--
|
||||
component juart_rx
|
||||
Port
|
||||
(
|
||||
rst : in std_logic;
|
||||
clk : in std_logic;
|
||||
ser_in : in std_logic;
|
||||
dout : out unsigned(7 downto 0);
|
||||
dout_vld : out std_logic;
|
||||
en_16_x_baud : in std_logic
|
||||
);
|
||||
end component;
|
||||
--
|
||||
-- 'Bucket Brigade' FIFO
|
||||
--
|
||||
component bbfifo
|
||||
Generic
|
||||
(
|
||||
depth_bits : integer := 4;
|
||||
data_width : integer := 8
|
||||
);
|
||||
Port
|
||||
(
|
||||
rst : in std_logic;
|
||||
clk : in std_logic;
|
||||
we : in std_logic;
|
||||
din : in unsigned(7 downto 0);
|
||||
full : out std_logic;
|
||||
half_full : out std_logic;
|
||||
re : in std_logic;
|
||||
dout : out unsigned(7 downto 0);
|
||||
dout_vld : out std_logic
|
||||
);
|
||||
end component;
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
-- Signals used in UART_TX
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
signal uart_data_out : unsigned(7 downto 0);
|
||||
signal fifo_write : std_logic;
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
-- Start of UART_TX circuit description
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
begin
|
||||
|
||||
juart: juart_rx
|
||||
port map
|
||||
(
|
||||
rst => rst,
|
||||
clk => clk,
|
||||
en_16_x_baud => en_16_x_baud,
|
||||
dout_vld => fifo_write,
|
||||
dout => uart_data_out,
|
||||
ser_in => ser_in
|
||||
);
|
||||
|
||||
|
||||
buf: bbfifo
|
||||
GENERIC MAP
|
||||
(
|
||||
depth_bits => fifo_depth_bits,
|
||||
data_width => 8
|
||||
)
|
||||
port map
|
||||
(
|
||||
clk => clk,
|
||||
rst => rst,
|
||||
din => uart_data_out,
|
||||
dout => dout,
|
||||
we => fifo_write,
|
||||
re => re,
|
||||
full => full,
|
||||
half_full => half_full,
|
||||
dout_vld => dout_vld
|
||||
);
|
||||
|
||||
end rtl;
|
||||
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
-- END OF FILE UART_TX.VHD
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
|
||||
@@ -0,0 +1,140 @@
|
||||
-- UART Transmitter with integral 16 byte FIFO buffer
|
||||
--
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
use IEEE.numeric_std.ALL;
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
-- Main Entity for UART_TX
|
||||
--
|
||||
entity uart_tx is
|
||||
Generic
|
||||
(
|
||||
fifo_depth_bits : integer := 4
|
||||
);
|
||||
Port
|
||||
(
|
||||
rst : in std_logic;
|
||||
clk : in std_logic;
|
||||
we : in std_logic;
|
||||
din : in unsigned(7 downto 0);
|
||||
full : out std_logic;
|
||||
half_full : out std_logic;
|
||||
ser_out : out std_logic;
|
||||
tx_complete : out std_logic;
|
||||
tx_empty : out std_logic;
|
||||
en_16_x_baud : in std_logic
|
||||
);
|
||||
end uart_tx;
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
-- Start of Main Architecture for UART_TX
|
||||
--
|
||||
architecture rtl of uart_tx is
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
-- Components used in UART_TX and defined in subsequent entities.
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
-- Constant (K) Compact UART Transmitter
|
||||
--
|
||||
component juart_tx
|
||||
Port
|
||||
(
|
||||
rst : in std_logic;
|
||||
clk : in std_logic;
|
||||
din : in unsigned(7 downto 0);
|
||||
we : in std_logic;
|
||||
en_16_x_baud : in std_logic;
|
||||
ser_out : out std_logic;
|
||||
Tx_complete : out std_logic
|
||||
);
|
||||
end component;
|
||||
--
|
||||
-- 'Bucket Brigade' FIFO
|
||||
--
|
||||
component bbfifo
|
||||
Generic
|
||||
(
|
||||
depth_bits : integer := 4;
|
||||
data_width : integer := 8
|
||||
);
|
||||
Port
|
||||
(
|
||||
rst : in std_logic;
|
||||
clk : in std_logic;
|
||||
we : in std_logic;
|
||||
din : in unsigned(7 downto 0);
|
||||
full : out std_logic;
|
||||
half_full : out std_logic;
|
||||
re : in std_logic;
|
||||
dout : out unsigned(7 downto 0);
|
||||
dout_vld : out std_logic
|
||||
);
|
||||
end component;
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
-- Signals used in UART_TX
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
signal fifo_data_out : unsigned(7 downto 0);
|
||||
signal fifo_data_present : std_logic;
|
||||
signal fifo_read : std_logic;
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
-- Start of UART_TX circuit description
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
begin
|
||||
|
||||
tx_complete <= fifo_read;
|
||||
tx_empty <= not fifo_data_present;
|
||||
|
||||
juart: juart_tx
|
||||
port map
|
||||
(
|
||||
rst => rst,
|
||||
clk => clk,
|
||||
din => fifo_data_out,
|
||||
we => fifo_data_present,
|
||||
en_16_x_baud => en_16_x_baud,
|
||||
ser_out => ser_out,
|
||||
Tx_complete => fifo_read
|
||||
);
|
||||
|
||||
|
||||
buf: bbfifo
|
||||
GENERIC MAP
|
||||
(
|
||||
depth_bits => fifo_depth_bits,
|
||||
data_width => 8
|
||||
)
|
||||
port map
|
||||
(
|
||||
clk => clk,
|
||||
rst => rst,
|
||||
din => din,
|
||||
dout => fifo_data_out,
|
||||
we => we,
|
||||
re => fifo_read,
|
||||
full => full,
|
||||
half_full => half_full,
|
||||
dout_vld => fifo_data_present
|
||||
);
|
||||
|
||||
end rtl;
|
||||
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
-- END OF FILE UART_TX.VHD
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
|
||||
Reference in New Issue
Block a user