jens/vhdl
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

- refactored

Browse Source 
git-svn-id: http://moon:8086/svn/vhdl/trunk@1483 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
jens
2021-03-23 11:41:42 +00:00
parent a1df4a5323
commit d249d20b50
19 changed files with 0 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files
lib/uart/src/generic/juart/juart_rx.vhd
+184
View File
@@ -0,0 +1,184 @@
-- UART Receiver
--
-- Version : 1.00
-- Version Date : 15 December 2016
--
------------------------------------------------------------------------------------
--
-- Library declarations
--
-- The Unisim Library is used to define Xilinx primitives. It is also used during
-- simulation. The source can be viewed at %XILINX%\vhdl\src\unisims\unisim_VCOMP.vhd
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;
--
------------------------------------------------------------------------------------
--
-- Main Entity
--
entity juart_rx is
Port
(
rst : in std_logic;
clk : in std_logic;
ser_in : in std_logic;
dout : out unsigned(7 downto 0);
dout_vld : out std_logic;
en_16_x_baud : in std_logic
);
end juart_rx;
--
------------------------------------------------------------------------------------
--
-- Start of Main Architecture
--
architecture behavior of juart_rx is
--
------------------------------------------------------------------------------------
--
------------------------------------------------------------------------------------
--
-- Signals used
--
------------------------------------------------------------------------------------
--
constant OVERSAMPLING : natural := 16;
subtype bit_count_t is natural range 0 to OVERSAMPLING-1;
signal bit_count_rst : std_logic;
signal bit_count : bit_count_t;
signal data_valid : std_logic;
signal shiftreg_en : std_logic;
signal shiftreg : unsigned (7 downto 0);
signal sample_count_rst : std_logic;
signal sample_count : natural range 0 to OVERSAMPLING-1;
signal bit_sample : std_logic;
type state_t is (idle, wait_start, start, shift, stop);
signal state : state_t;
signal state_next : state_t;
--
--
begin
data_out_reg:
process(clk)
begin
if rising_edge(clk) then
dout_vld <= '0';
if data_valid = '1' then
dout <= shiftreg;
dout_vld <= '1';
end if;
end if;
end process;
proc_state_next:
process(clk)
begin
if rising_edge(clk) then
if rst = '1' then
state <= idle;
else
state <= state_next;
end if;
end if;
end process;
statemachine:
process(state, bit_count, bit_sample, ser_in)
begin
state_next <= state;
sample_count_rst <= '0';
bit_count_rst <= '0';
shiftreg_en <= '0';
data_valid <= '0';
case state is
when idle =>
if ser_in = '1' then
state_next <= wait_start;
end if;
when wait_start =>
sample_count_rst <= '1';
if ser_in = '0' then
state_next <= start;
end if;
when start =>
bit_count_rst <= '1';
if bit_sample = '1' then
state_next <= shift;
end if;
when shift =>
shiftreg_en <= '1';
if bit_count = 8 then
state_next <= stop;
end if;
when stop =>
if bit_sample = '1' then
state_next <= idle;
data_valid <= '1';
end if;
when others =>
state_next <= idle;
end case;
end process;
shift_register:
process(clk)
begin
if rising_edge(clk) then
if rst = '1' then
shiftreg <= (others => '0');
elsif shiftreg_en = '1' and bit_sample = '1' then
shiftreg <= ser_in & shiftreg(shiftreg'left downto 1);
end if;
end if;
end process;
sample_counter:
process(clk)
begin
if rising_edge(clk) then
bit_sample <= '0';
if sample_count_rst = '1' then
sample_count <= 0;
elsif en_16_x_baud = '1' then
if sample_count /= OVERSAMPLING-1 then
sample_count <= sample_count + 1;
else
sample_count <= 0;
end if;
if sample_count = OVERSAMPLING/2-1 then
bit_sample <= '1';
end if;
end if;
end if;
end process;
bit_counter:
process(clk)
begin
if rising_edge(clk) then
if bit_count_rst = '1' then
bit_count <= 0;
elsif bit_count /= bit_count_t'high and bit_sample = '1' then
bit_count <= bit_count + 1;
end if;
end if;
end process;
end behavior;
------------------------------------------------------------------------------------
--
-- END OF FILE
--
------------------------------------------------------------------------------------
lib/uart/src/generic/juart/juart_tx.vhd
+126
View File
@@ -0,0 +1,126 @@
-- UART Transmitter
--
-- Version : 1.00
-- Version Date : 15 December 2016
--
------------------------------------------------------------------------------------
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;
--
------------------------------------------------------------------------------------
--
-- Main Entity
--
entity juart_tx is
Port
(
rst : in std_logic;
clk : in std_logic;
we : in std_logic;
din : in unsigned(7 downto 0);
en_16_x_baud : in std_logic;
Tx_complete : out std_logic;
ser_out : out std_logic
);
end juart_tx;
--
------------------------------------------------------------------------------------
--
-- Start of Main Architecture
--
architecture behavior of juart_tx is
--
------------------------------------------------------------------------------------
--
------------------------------------------------------------------------------------
--
-- Signals used
--
------------------------------------------------------------------------------------
--
signal dinreg : unsigned (7 downto 0);
signal shiftreg : unsigned (9 downto 0);
signal busy : std_logic;
signal start : std_logic;
signal shift_enable : std_logic;
signal shift_enable_count : unsigned (3 downto 0);
signal bit_count : unsigned (3 downto 0);
--
--
begin
ser_out <= shiftreg(0);
Tx_complete <= not busy;
shift_enable_counter:
process(clk)
begin
if rising_edge(clk) then
shift_enable <= '0';
if rst = '1' then
shift_enable_count <= (others => '1');
elsif en_16_x_baud = '1' then
if shift_enable_count = 0 then
shift_enable <= '1';
shift_enable_count <= (others => '1');
else
shift_enable_count <= shift_enable_count - 1;
end if;
end if;
end if;
end process;
bit_counter:
process(clk)
begin
if rising_edge(clk) then
if start = '1' then
bit_count <= to_unsigned(shiftreg'length-1, bit_count'length);
elsif shift_enable = '1' then
if not (bit_count = 0) then
bit_count <= bit_count - 1;
end if;
end if;
end if;
end process;
transmit:
process(clk)
begin
if rising_edge(clk) then
if rst = '1' then
shiftreg <= (others => '1');
busy <= '0';
start <= '0';
elsif busy = '0' then
if we = '1' then
busy <= '1';
start <= '1';
dinreg <= din;
end if;
elsif shift_enable = '1' then
if start = '1' then
start <= '0';
shiftreg <= '1' & dinreg & '0';
elsif bit_count /= 0 then
shiftreg <= '1' & shiftreg(shiftreg'left downto 1);
if bit_count = 1 then
busy <= '0';
end if;
end if;
end if;
end if;
end process;
end behavior;
------------------------------------------------------------------------------------
--
-- END OF FILE
--
------------------------------------------------------------------------------------
lib/uart/src/generic/juart/tb_juart_rx.vhd
+123
View File
@@ -0,0 +1,123 @@
-------------------------------------------------------------------------
-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
-- This file: cpu_embedded using cpu_core and rom
--
-- Copyright (C) 2007 J. Ahrensfeld
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- For questions and ideas, please contact the author at jens@jayfield.org
--
--------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;
entity tb_juart_rx is
end;
architecture behave of tb_juart_rx is
-- Number of user data words for simulation
constant CLK_PERIOD : time := 10 ns;
constant BAUD_DIV : natural := 2;
signal rst : std_logic := '1';
signal clk : std_logic := '1';
signal en_16_x_baud : std_logic := '1';
signal ser_in : std_logic := '1';
signal dout_vld : std_logic;
signal dout : unsigned(7 downto 0);
signal serial_word : unsigned(7 downto 0) := X"AA";
signal baud_count : unsigned(15 downto 0);
signal baud_reg : unsigned(15 downto 0) := to_unsigned(BAUD_DIV-1, baud_count'length);
signal data_reg : unsigned(7 downto 0);
begin
dut : entity work.juart_rx
PORT MAP
(
rst => rst,
clk => clk,
en_16_x_baud => en_16_x_baud,
dout_vld => dout_vld,
dout => dout,
ser_in => ser_in
);
CLK_GEN: process
begin
wait for CLK_PERIOD/2;
clk <= not clk;
end process;
PROC_DATAREG: process
begin
wait until rising_edge(clk) and dout_vld = '1';
data_reg <= dout;
end process;
baud_timer:
process(clk)
begin
if rising_edge(clk) then
en_16_x_baud <= '0';
if rst = '1' then
baud_count <= (others => '0');
elsif baud_count = baud_reg then
baud_count <= (others => '0');
en_16_x_baud <= '1';
else
baud_count <= baud_count + 1;
end if;
end if;
end process;
------------------------------------------------------------------------------------------
STIMULUS: process
begin
wait for 3*CLK_PERIOD;
rst <= '0';
serial_word <= X"AA";
wait for 16*baud_div*CLK_PERIOD;
ser_in <= '0';
wait for 16*baud_div*CLK_PERIOD;
for i in serial_word'length-1 downto 0 loop
ser_in <= serial_word(i);
wait for 16*baud_div*CLK_PERIOD;
end loop;
ser_in <= '1';
wait for 16*baud_div*CLK_PERIOD;
serial_word <= X"55";
ser_in <= '0';
wait for 16*baud_div*CLK_PERIOD;
for i in serial_word'length-1 downto 0 loop
ser_in <= serial_word(i);
wait for 16*baud_div*CLK_PERIOD;
end loop;
ser_in <= '1';
wait;
end process;
end architecture behave;
lib/uart/src/generic/juart/tb_juart_tx.vhd
+115
View File
@@ -0,0 +1,115 @@
-------------------------------------------------------------------------
-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
-- This file: cpu_embedded using cpu_core and rom
--
-- Copyright (C) 2007 J. Ahrensfeld
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- For questions and ideas, please contact the author at jens@jayfield.org
--
--------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;
entity tb_juart_tx is
end;
architecture behave of tb_juart_tx is
-- Number of user data words for simulation
constant CLK_PERIOD : time := 10 ns;
constant BAUD_DIV : natural := 2;
signal rst : std_logic := '1';
signal clk : std_logic := '1';
signal en_16_x_baud : std_logic := '1';
signal we : std_logic := '0';
signal ser_out : std_logic;
signal Tx_complete : std_logic;
signal din : unsigned(7 downto 0) := (others => '0');
signal baud_count : unsigned(15 downto 0);
signal baud_reg : unsigned(15 downto 0) := to_unsigned(BAUD_DIV-1, baud_count'length);
begin
dut : entity work.juart_tx
PORT MAP
(
rst => rst,
clk => clk,
we => we,
din => din,
en_16_x_baud => en_16_x_baud,
Tx_complete => Tx_complete,
ser_out => ser_out
);
CLK_GEN: process
begin
wait for CLK_PERIOD/2;
clk <= not clk;
end process;
baud_timer:
process(clk)
begin
if rising_edge(clk) then
en_16_x_baud <= '0';
if rst = '1' then
baud_count <= (others => '0');
elsif baud_count = baud_reg then
baud_count <= (others => '0');
en_16_x_baud <= '1';
else
baud_count <= baud_count + 1;
end if;
end if;
end process;
------------------------------------------------------------------------------------------
STIMULUS: process
begin
wait for 3*CLK_PERIOD;
rst <= '0';
wait for 3*CLK_PERIOD;
wait until rising_edge(clk);
din <= X"A5";
wait until rising_edge(clk) and Tx_complete = '1';
we <= '1';
wait until rising_edge(clk) and Tx_complete = '0';
we <= '0';
wait until rising_edge(clk) and Tx_complete = '1';
din <= X"AA";
wait until rising_edge(clk) and Tx_complete = '1';
we <= '1';
wait until rising_edge(clk) and Tx_complete = '0';
we <= '0';
din <= X"55";
wait until rising_edge(clk) and Tx_complete = '1';
we <= '1';
wait until rising_edge(clk) and Tx_complete = '0';
we <= '0';
wait;
end process;
end architecture behave;
lib/uart/src/generic/juart/tb_juart_tx_rx.vhd
+144
View File
@@ -0,0 +1,144 @@
-------------------------------------------------------------------------
-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
-- This file: cpu_embedded using cpu_core and rom
--
-- Copyright (C) 2007 J. Ahrensfeld
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- For questions and ideas, please contact the author at jens@jayfield.org
--
--------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;
entity tb_juart_tx_rx is
end;
architecture behave of tb_juart_tx_rx is
-- Number of user data words for simulation
constant CLK_PERIOD : time := 10 ns;
constant BAUD_DIV : natural := 2;
-- Common
signal rst : std_logic := '1';
signal clk : std_logic := '1';
signal en_16_x_baud : std_logic := '1';
-- TX
signal tx_we : std_logic := '0';
signal ser_out : std_logic;
signal Tx_complete : std_logic;
signal tx_din : unsigned(7 downto 0) := (others => '0');
-- RX
signal ser_in : std_logic := '1';
signal rx_dout_vld : std_logic;
signal rx_dout : unsigned(7 downto 0);
-- Others
signal baud_count : unsigned(15 downto 0);
signal baud_reg : unsigned(15 downto 0) := to_unsigned(BAUD_DIV-1, baud_count'length);
signal data_rx : unsigned(7 downto 0);
signal data_tx : unsigned(7 downto 0);
begin
ser_in <= ser_out;
inst_juart_tx : entity work.juart_tx
PORT MAP
(
rst => rst,
clk => clk,
we => tx_we,
din => tx_din,
en_16_x_baud => en_16_x_baud,
Tx_complete => Tx_complete,
ser_out => ser_out
);
inst_juart_rx : entity work.juart_rx
PORT MAP
(
rst => rst,
clk => clk,
en_16_x_baud => en_16_x_baud,
dout_vld => rx_dout_vld,
dout => rx_dout,
ser_in => ser_in
);
CLK_GEN: process
begin
wait for CLK_PERIOD/2;
clk <= not clk;
end process;
PROC_DATAREG_RX: process
begin
wait until rising_edge(clk) and rx_dout_vld = '1';
data_rx <= rx_dout;
assert rx_dout = data_tx report "Data mismatch" severity failure;
end process;
PROC_DATAREG_TX: process
begin
wait until rising_edge(clk) and tx_we = '1';
data_tx <= tx_din;
end process;
baud_timer:
process(clk)
begin
if rising_edge(clk) then
en_16_x_baud <= '0';
if rst = '1' then
baud_count <= (others => '0');
elsif baud_count = baud_reg then
baud_count <= (others => '0');
en_16_x_baud <= '1';
else
baud_count <= baud_count + 1;
end if;
end if;
end process;
------------------------------------------------------------------------------------------
STIMULUS: process
begin
wait for 3*CLK_PERIOD;
rst <= '0';
wait for 3*CLK_PERIOD;
wait until rising_edge(clk);
for i in 0 to 255 loop
wait until rising_edge(clk) and Tx_complete = '1';
tx_din <= to_unsigned(i, 8);
tx_we <= '1';
wait until rising_edge(clk) and Tx_complete = '0';
tx_we <= '0';
end loop;
wait;
end process;
end architecture behave;
lib/uart/src/generic/uart.vhd
+112
View File
@@ -0,0 +1,112 @@
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
LIBRARY WORK;
USE WORK.uart_types.all;
------------------------------------------------------------------------------------
ENTITY uart IS
Generic
(
fifo_depth_bits : integer := 4
);
Port
(
clk : in STD_LOGIC;
rst : in STD_LOGIC;
we : in STD_LOGIC;
re : in STD_LOGIC;
din : in unsigned(7 downto 0);
dout : out unsigned(7 downto 0);
ser_rx : in std_logic;
ser_tx : out std_logic;
ctrl : in ctrl_t;
status : out status_t
);
END uart;
ARCHITECTURE rtl OF uart IS
signal baud_count : unsigned(15 downto 0);
signal en_16_x_baud : std_logic;
signal rx_dout_vld : std_logic;
signal rx_full : std_logic;
signal rx_half_full : std_logic;
signal tx_complete : std_logic;
signal tx_empty : std_logic;
signal tx_full : std_logic;
signal tx_half_full : std_logic;
begin
baud_timer:
process(clk)
begin
if rising_edge(clk) then
en_16_x_baud <= '0';
if rst = '1' then
baud_count <= (others => '0');
elsif baud_count = ctrl.baudrate then
baud_count <= (others => '0');
en_16_x_baud <= '1';
else
baud_count <= baud_count + 1;
end if;
end if;
end process;
inst_uart_tx : entity work.uart_tx
GENERIC MAP
(
fifo_depth_bits => fifo_depth_bits
)
PORT MAP
(
rst => rst,
clk => clk,
we => we,
din => din,
en_16_x_baud => en_16_x_baud,
full => tx_full,
half_full => tx_half_full,
tx_complete => tx_complete,
tx_empty => tx_empty,
ser_out => ser_tx
);
inst_uart_rx : entity work.uart_rx
GENERIC MAP
(
fifo_depth_bits => fifo_depth_bits
)
PORT MAP
(
rst => rst,
clk => clk,
en_16_x_baud => en_16_x_baud,
dout_vld => rx_dout_vld,
dout => dout,
re => re,
full => rx_full,
half_full => rx_half_full,
ser_in => ser_rx
);
-- Status
status.rx_present <= rx_dout_vld;
status.tx_complete <= tx_complete;
status.tx_empty <= tx_empty;
status.tx_full <= tx_full;
end rtl;
------------------------------------------------------------------------------------
--
-- END OF FILE UART_RX.VHD
--
------------------------------------------------------------------------------------
lib/uart/src/generic/uart_rx.vhd
+133
View File
@@ -0,0 +1,133 @@
-- UART Receiver with integral 16 byte FIFO buffer
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;
--
------------------------------------------------------------------------------------
--
-- Main Entity for UART_TX
--
entity uart_rx is
Generic
(
fifo_depth_bits : integer := 4
);
Port
(
rst : in std_logic;
clk : in std_logic;
re : in std_logic;
full : out std_logic;
half_full : out std_logic;
ser_in : in std_logic;
dout_vld : out std_logic;
dout : out unsigned(7 downto 0);
en_16_x_baud : in std_logic
);
end uart_rx;
--
------------------------------------------------------------------------------------
--
-- Start of Main Architecture for UART_TX
--
architecture rtl of uart_rx is
--
------------------------------------------------------------------------------------
--
-- Components used in UART_TX and defined in subsequent entities.
--
------------------------------------------------------------------------------------
--
-- Constant (K) Compact UART Transmitter
--
component juart_rx
Port
(
rst : in std_logic;
clk : in std_logic;
ser_in : in std_logic;
dout : out unsigned(7 downto 0);
dout_vld : out std_logic;
en_16_x_baud : in std_logic
);
end component;
--
-- 'Bucket Brigade' FIFO
--
component bbfifo
Generic
(
depth_bits : integer := 4;
data_width : integer := 8
);
Port
(
rst : in std_logic;
clk : in std_logic;
we : in std_logic;
din : in unsigned(7 downto 0);
full : out std_logic;
half_full : out std_logic;
re : in std_logic;
dout : out unsigned(7 downto 0);
dout_vld : out std_logic
);
end component;
--
------------------------------------------------------------------------------------
--
-- Signals used in UART_TX
--
------------------------------------------------------------------------------------
--
signal uart_data_out : unsigned(7 downto 0);
signal fifo_write : std_logic;
--
------------------------------------------------------------------------------------
--
-- Start of UART_TX circuit description
--
------------------------------------------------------------------------------------
--
begin
juart: juart_rx
port map
(
rst => rst,
clk => clk,
en_16_x_baud => en_16_x_baud,
dout_vld => fifo_write,
dout => uart_data_out,
ser_in => ser_in
);
buf: bbfifo
GENERIC MAP
(
depth_bits => fifo_depth_bits,
data_width => 8
)
port map
(
clk => clk,
rst => rst,
din => uart_data_out,
dout => dout,
we => fifo_write,
re => re,
full => full,
half_full => half_full,
dout_vld => dout_vld
);
end rtl;
------------------------------------------------------------------------------------
--
-- END OF FILE UART_TX.VHD
--
------------------------------------------------------------------------------------
lib/uart/src/generic/uart_tx.vhd
+140
View File
@@ -0,0 +1,140 @@
-- UART Transmitter with integral 16 byte FIFO buffer
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;
--
------------------------------------------------------------------------------------
--
-- Main Entity for UART_TX
--
entity uart_tx is
Generic
(
fifo_depth_bits : integer := 4
);
Port
(
rst : in std_logic;
clk : in std_logic;
we : in std_logic;
din : in unsigned(7 downto 0);
full : out std_logic;
half_full : out std_logic;
ser_out : out std_logic;
tx_complete : out std_logic;
tx_empty : out std_logic;
en_16_x_baud : in std_logic
);
end uart_tx;
--
------------------------------------------------------------------------------------
--
-- Start of Main Architecture for UART_TX
--
architecture rtl of uart_tx is
--
------------------------------------------------------------------------------------
--
-- Components used in UART_TX and defined in subsequent entities.
--
------------------------------------------------------------------------------------
--
-- Constant (K) Compact UART Transmitter
--
component juart_tx
Port
(
rst : in std_logic;
clk : in std_logic;
din : in unsigned(7 downto 0);
we : in std_logic;
en_16_x_baud : in std_logic;
ser_out : out std_logic;
Tx_complete : out std_logic
);
end component;
--
-- 'Bucket Brigade' FIFO
--
component bbfifo
Generic
(
depth_bits : integer := 4;
data_width : integer := 8
);
Port
(
rst : in std_logic;
clk : in std_logic;
we : in std_logic;
din : in unsigned(7 downto 0);
full : out std_logic;
half_full : out std_logic;
re : in std_logic;
dout : out unsigned(7 downto 0);
dout_vld : out std_logic
);
end component;
--
------------------------------------------------------------------------------------
--
-- Signals used in UART_TX
--
------------------------------------------------------------------------------------
--
signal fifo_data_out : unsigned(7 downto 0);
signal fifo_data_present : std_logic;
signal fifo_read : std_logic;
--
------------------------------------------------------------------------------------
--
-- Start of UART_TX circuit description
--
------------------------------------------------------------------------------------
--
begin
tx_complete <= fifo_read;
tx_empty <= not fifo_data_present;
juart: juart_tx
port map
(
rst => rst,
clk => clk,
din => fifo_data_out,
we => fifo_data_present,
en_16_x_baud => en_16_x_baud,
ser_out => ser_out,
Tx_complete => fifo_read
);
buf: bbfifo
GENERIC MAP
(
depth_bits => fifo_depth_bits,
data_width => 8
)
port map
(
clk => clk,
rst => rst,
din => din,
dout => fifo_data_out,
we => we,
re => fifo_read,
full => full,
half_full => half_full,
dout_vld => fifo_data_present
);
end rtl;
------------------------------------------------------------------------------------
--
-- END OF FILE UART_TX.VHD
--
------------------------------------------------------------------------------------
lib/uart/src/sim/uart.vhd
+69
View File
@@ -0,0 +1,69 @@
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
LIBRARY WORK;
USE WORK.uart_types.all;
use std.textio.all; -- Imports the standard textio package.
------------------------------------------------------------------------------------
ENTITY uart IS
Generic
(
fifo_depth_bits : integer := 4
);
Port
(
clk : in STD_LOGIC;
rst : in STD_LOGIC;
we : in STD_LOGIC;
re : in STD_LOGIC;
din : in unsigned(7 downto 0);
dout : out unsigned(7 downto 0);
ser_rx : in std_logic;
ser_tx : out std_logic;
ctrl : in ctrl_t;
status : out status_t
);
END uart;
ARCHITECTURE simulation OF uart IS
begin
-- RX
dout <= X"00";
status.rx_present <= '0';
-- TX
ser_tx <= '1';
status.tx_complete <= '1';
status.tx_empty <= '1';
status.tx_full <= '0';
proc_tx:
process(clk)
file output: text open write_mode is "STD_OUTPUT";
variable L : line;
begin
if rising_edge(clk) then
if we = '1' then
if din /= X"0D" then
write(L, character'val(to_integer(din)));
end if;
if din = X"0A" then
writeline(output, L);
end if;
end if;
end if;
end process;
end simulation;
------------------------------------------------------------------------------------
--
-- END OF FILE UART_RX.VHD
--
------------------------------------------------------------------------------------
lib/uart/src/tb_uart.vhd
+136
View File
@@ -0,0 +1,136 @@
-------------------------------------------------------------------------
-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
-- This file: cpu_embedded using cpu_core and rom
--
-- Copyright (C) 2007 J. Ahrensfeld
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- For questions and ideas, please contact the author at jens@jayfield.org
--
--------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;
LIBRARY WORK;
USE WORK.uart_types.all;
entity tb_uart is
end;
architecture behave of tb_uart is
-- Number of user data words for simulation
constant CLK_PERIOD : time := 10 ns;
constant BAUD_DIV : natural := 2;
-- Common
signal rst : std_logic := '1';
signal clk : std_logic := '1';
signal ctrl : ctrl_t;
signal status : status_t;
-- TX
signal tx_we : std_logic := '0';
signal tx_ser : std_logic;
signal tx_din : unsigned(7 downto 0) := (others => '0');
-- RX
signal rx_re : std_logic := '0';
signal rx_ser : std_logic := '1';
signal rx_dout : unsigned(7 downto 0);
-- Others
signal data_rx : unsigned(7 downto 0);
signal data_tx : unsigned(7 downto 0);
signal count_rx : natural;
begin
rx_ser <= tx_ser;
ctrl.baudrate <= to_unsigned(BAUD_DIV-1, ctrl.baudrate'length);
dut : entity work.uart
PORT MAP
(
rst => rst,
clk => clk,
we => tx_we,
re => rx_re,
din => tx_din,
dout => rx_dout,
ser_tx => tx_ser,
ser_rx => rx_ser,
ctrl => ctrl,
status => status
);
CLK_GEN: process
begin
wait for CLK_PERIOD/2;
clk <= not clk;
end process;
PROC_DATAREG_RX:
process (clk)
begin
if rising_edge(clk) then
if rst = '1' then
count_rx <= 0;
elsif status.rx_present = '1' and rx_re = '1' then
-- assert rx_dout = count_rx report "Data mismatch" severity failure;
data_rx <= rx_dout;
count_rx <= count_rx + 1;
end if;
end if;
end process;
PROC_RX_RE: process
begin
wait for 10 us;
rx_re <= status.rx_present;
end process;
PROC_DATAREG_TX: process
begin
wait until rising_edge(clk) and tx_we = '1';
data_tx <= tx_din;
end process;
------------------------------------------------------------------------------------------
STIMULUS: process
begin
wait for 3*CLK_PERIOD;
rst <= '0';
wait for 3*CLK_PERIOD;
wait until rising_edge(clk);
for i in 0 to 255 loop
wait until rising_edge(clk);
tx_din <= to_unsigned(i, 8);
tx_we <= '1';
wait until rising_edge(clk) and status.tx_full = '0';
tx_we <= '0';
end loop;
wait;
end process;
end architecture behave;
lib/uart/src/uart_jtag.vhd
+159
View File
@@ -0,0 +1,159 @@
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
LIBRARY WORK;
USE WORK.uart_types.all;
LIBRARY work;
use work.utils_pkg.all;
------------------------------------------------------------------------------------
ENTITY uart IS
Generic
(
FIFO_DEPTH_RX : positive := 16;
FIFO_DEPTH_TX : positive := 16
);
Port
(
clk : in STD_LOGIC;
rst : in STD_LOGIC;
we : in STD_LOGIC;
re : in STD_LOGIC;
din : in unsigned(7 downto 0);
dout : out unsigned(7 downto 0);
ser_rx : in std_logic;
ser_tx : out std_logic;
ctrl : in ctrl_t;
status : out status_t
);
END uart;
ARCHITECTURE jtag OF uart IS
subtype addr_t is unsigned (2 downto 0);
subtype reg_t is unsigned (7 downto 0);
signal jtag_addr : addr_t;
signal jtag_din : reg_t;
signal jtag_dout : reg_t;
signal jtag_we : STD_LOGIC;
signal jtag_re : STD_LOGIC;
signal rx_fifo_dout : reg_t;
signal rx_fifo_full : STD_LOGIC;
signal rx_fifo_empty : STD_LOGIC;
signal tx_fifo_dout : reg_t;
signal tx_fifo_full : STD_LOGIC;
signal tx_fifo_empty : STD_LOGIC;
signal rx_data_cs : STD_LOGIC;
signal tx_data_cs : STD_LOGIC;
signal rx_data_we : STD_LOGIC;
signal tx_data_re : STD_LOGIC;
begin
status.rx_present <= not rx_fifo_empty;
status.tx_complete <= '1';
status.tx_empty <= tx_fifo_empty;
status.tx_full <= tx_fifo_full;
inst_jtag_reg: entity work.jtag_reg
GENERIC MAP
(
INSTANCE_INDEX => 0,
DATA_WIDTH => reg_t'length, -- bits
ADDR_WIDTH => addr_t'length -- bits
)
PORT MAP
(
rst => rst,
clk => clk,
addr_o => jtag_addr,
reg_i => jtag_din,
reg_o => jtag_dout,
we_o => jtag_we,
re_o => jtag_re
);
rx_data_we <= rx_data_cs and jtag_we;
inst_rx_fifo: entity work.fifo_sync
Generic map
(
addr_width => NextExpBaseTwo(FIFO_DEPTH_RX),
data_width => reg_t'length
)
Port map
(
rst => rst,
clk => clk,
we => rx_data_we,
re => re,
fifo_full => rx_fifo_full,
fifo_empty => rx_fifo_empty,
data_w => jtag_dout,
data_r => dout
);
tx_data_re <= tx_data_cs and jtag_re;
inst_tx_fifo: entity work.fifo_sync
Generic map
(
addr_width => NextExpBaseTwo(FIFO_DEPTH_TX),
data_width => reg_t'length
)
Port map
(
rst => rst,
clk => clk,
we => we,
re => tx_data_re,
fifo_full => tx_fifo_full,
fifo_empty => tx_fifo_empty,
data_w => din,
data_r => tx_fifo_dout
);
-- JTAG Registers
process(jtag_addr, tx_fifo_empty, rx_fifo_dout, tx_fifo_dout)
begin
rx_data_cs <= '0';
tx_data_cs <= '0';
jtag_din <= "0000000" & tx_fifo_empty;
case jtag_addr is
-- Reg #0
when "000" => null; -- Status
-- Reg #1
when "001" => -- RX-Data
rx_data_cs <= '1';
jtag_din <= rx_fifo_dout;
-- Reg #2
when "010" => -- TX-Data
tx_data_cs <= '1';
jtag_din <= tx_fifo_dout;
when others => null;
end case;
end process;
end jtag;
------------------------------------------------------------------------------------
--
-- END OF FILE UART_RX.VHD
--
------------------------------------------------------------------------------------
lib/uart/src/uart_types.vhd
+18
View File
@@ -0,0 +1,18 @@
library IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
package uart_types is
type ctrl_t is record
baudrate : unsigned(15 downto 0);
end record;
type status_t is record
rx_present : STD_LOGIC;
tx_complete : STD_LOGIC;
tx_empty : STD_LOGIC;
tx_full : STD_LOGIC;
end record;
end uart_types;
lib/uart/src/uart_wb.vhd
+166
View File
@@ -0,0 +1,166 @@
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
LIBRARY WORK;
USE WORK.uart_types.all;
ENTITY uart_wb IS
Generic
(
f_sysclk : real := 100.0;
baudrate_default : real := 115200.0;
fifo_depth_bits : integer := 4
);
Port
(
CLK_I : in STD_LOGIC;
RST_I : in STD_LOGIC;
INT_O : out STD_LOGIC;
CYC_I : in STD_LOGIC;
STB_I : in STD_LOGIC;
SEL_I : in unsigned(3 downto 0);
WE_I : in STD_LOGIC;
ACK_O : out STD_LOGIC;
SRDY_O : out STD_LOGIC;
MRDY_I : in STD_LOGIC;
ADDR_I : in unsigned(31 downto 0);
DAT_I : in unsigned(31 downto 0);
DAT_O : out unsigned(31 downto 0);
ser_rx : in std_logic;
ser_tx : out std_logic
);
END uart_wb;
ARCHITECTURE rtl OF uart_wb IS
COMPONENT uart
Generic
(
fifo_depth_bits : integer
);
Port
(
clk : in STD_LOGIC;
rst : in STD_LOGIC;
we : in STD_LOGIC;
re : in STD_LOGIC;
din : in unsigned(7 downto 0);
dout : out unsigned(7 downto 0);
ser_rx : in std_logic;
ser_tx : out std_logic;
ctrl : in ctrl_t;
status : out status_t
);
END COMPONENT;
-- Signals for UART connections
signal reg_uart_baud : unsigned(15 downto 0);
signal reg_we_uart_tx : std_logic;
signal reg_re_uart_rx : std_logic;
signal reg_uart_tx : unsigned(7 downto 0);
signal reg_uart_rx : unsigned(7 downto 0);
signal uart_status_port : unsigned(15 downto 0);
signal rx_int_en : std_logic;
signal tx_int_en : std_logic;
signal irq_rx : std_logic;
signal irq_tx : std_logic;
signal ctrl : ctrl_t;
signal status : status_t;
begin
SRDY_O <= CYC_I;
ctrl.baudrate <= reg_uart_baud;
inst_uart : uart
GENERIC MAP
(
fifo_depth_bits => fifo_depth_bits
)
PORT MAP
(
clk => CLK_I,
rst => RST_I,
we => reg_we_uart_tx,
re => reg_re_uart_rx,
din => reg_uart_tx,
dout => reg_uart_rx,
ser_rx => ser_rx,
ser_tx => ser_tx,
ctrl => ctrl,
status => status
);
------------------------------------------------------------------
registers_write:
process(CLK_I)
begin
if rising_edge(CLK_I) then
reg_we_uart_tx <= '0';
if RST_I = '1' then
reg_uart_baud <= to_unsigned(integer(0.5+f_sysclk*1.0e6/(16.0*baudrate_default))-1, 16);
rx_int_en <= '0';
tx_int_en <= '0';
elsif (STB_I and CYC_I and WE_I) = '1' then
case ADDR_I(5 downto 2) is
when "0000" =>
reg_uart_tx <= DAT_I(7 downto 0);
reg_we_uart_tx <= '1';
when "0001" =>
rx_int_en <= DAT_I(6);
tx_int_en <= DAT_I(5);
when "0010" =>
reg_uart_baud <= DAT_I(15 downto 0);
when others => null;
end case;
end if;
end if;
end process;
registers_read:
process(CLK_I)
begin
if rising_edge(CLK_I) then
reg_re_uart_rx <= '0';
ACK_O <= '0';
if (STB_I and CYC_I) = '1' then
ACK_O <= not WE_I;
DAT_O <= (others => '0');
case ADDR_I(5 downto 2) is
when "0000" =>
reg_re_uart_rx <= not WE_I;
DAT_O(7 downto 0) <= reg_uart_rx;
when "0001" =>
DAT_O(15 downto 0) <= uart_status_port;
when "0010" =>
DAT_O(15 downto 0) <= reg_uart_baud;
when others => null;
end case;
end if;
end if;
end process;
irq_register:
process(CLK_I)
begin
if rising_edge(CLK_I) then
irq_tx <= status.tx_empty and tx_int_en;
irq_rx <= status.rx_present and rx_int_en;
end if;
end process;
uart_status_port <= "000000" & irq_rx & irq_tx & '0' & rx_int_en & tx_int_en & status.rx_present & '0' & '0' & status.tx_full & status.tx_full;
INT_O <= irq_rx or irq_tx;
end rtl;
lib/uart/src/xilinx/kcuart/bbfifo_16x8.vhd
+281
View File
@@ -0,0 +1,281 @@
-- 'Bucket Brigade' FIFO
-- 16 deep
-- 8-bit data
--
-- Version : 1.10
-- Version Date : 3rd December 2003
-- Reason : '--translate' directives changed to '--synthesis translate' directives
--
-- Version : 1.00
-- Version Date : 14th October 2002
--
-- Start of design entry : 14th October 2002
--
-- Ken Chapman
-- Xilinx Ltd
-- Benchmark House
-- 203 Brooklands Road
-- Weybridge
-- Surrey KT13 ORH
-- United Kingdom
--
-- chapman@xilinx.com
--
------------------------------------------------------------------------------------
--
-- NOTICE:
--
-- Copyright Xilinx, Inc. 2002. This code may be contain portions patented by other
-- third parties. By providing this core as one possible implementation of a standard,
-- Xilinx is making no representation that the provided implementation of this standard
-- is free from any claims of infringement by any third party. Xilinx expressly
-- disclaims any warranty with respect to the adequacy of the implementation, including
-- but not limited to any warranty or representation that the implementation is free
-- from claims of any third party. Futhermore, Xilinx is providing this core as a
-- courtesy to you and suggests that you contact all third parties to obtain the
-- necessary rights to use this implementation.
--
------------------------------------------------------------------------------------
--
-- Library declarations
--
-- The Unisim Library is used to define Xilinx primitives. It is also used during
-- simulation. The source can be viewed at %XILINX%\vhdl\src\unisims\unisim_VCOMP.vhd
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library unisim;
use unisim.vcomponents.all;
--
------------------------------------------------------------------------------------
--
-- Main Entity for BBFIFO_16x8
--
entity bbfifo_16x8 is
Port ( data_in : in std_logic_vector(7 downto 0);
data_out : out std_logic_vector(7 downto 0);
reset : in std_logic;
write : in std_logic;
read : in std_logic;
full : out std_logic;
half_full : out std_logic;
data_present : out std_logic;
clk : in std_logic);
end bbfifo_16x8;
--
------------------------------------------------------------------------------------
--
-- Start of Main Architecture for BBFIFO_16x8
--
architecture low_level_definition of bbfifo_16x8 is
--
------------------------------------------------------------------------------------
--
------------------------------------------------------------------------------------
--
-- Signals used in BBFIFO_16x8
--
------------------------------------------------------------------------------------
--
signal pointer : std_logic_vector(3 downto 0);
signal next_count : std_logic_vector(3 downto 0);
signal half_count : std_logic_vector(3 downto 0);
signal count_carry : std_logic_vector(2 downto 0);
signal pointer_zero : std_logic;
signal pointer_full : std_logic;
signal decode_data_present : std_logic;
signal data_present_int : std_logic;
signal valid_write : std_logic;
--
--
------------------------------------------------------------------------------------
--
-- Attributes to define LUT contents during implementation
-- The information is repeated in the generic map for functional simulation--
--
------------------------------------------------------------------------------------
--
attribute INIT : string;
attribute INIT of zero_lut : label is "0001";
attribute INIT of full_lut : label is "8000";
attribute INIT of dp_lut : label is "BFA0";
attribute INIT of valid_lut : label is "C4";
--
------------------------------------------------------------------------------------
--
-- Start of BBFIFO_16x8 circuit description
--
------------------------------------------------------------------------------------
--
begin
-- SRL16E data storage
data_width_loop: for i in 0 to 7 generate
--
attribute INIT : string;
attribute INIT of data_srl : label is "0000";
--
begin
data_srl: SRL16E
--synthesis translate_off
generic map (INIT => X"0000")
--synthesis translate_on
port map( D => data_in(i),
CE => valid_write,
CLK => clk,
A0 => pointer(0),
A1 => pointer(1),
A2 => pointer(2),
A3 => pointer(3),
Q => data_out(i) );
end generate data_width_loop;
-- 4-bit counter to act as data pointer
-- Counter is clock enabled by 'data_present'
-- Counter will be reset when 'reset' is active
-- Counter will increment when 'valid_write' is active
count_width_loop: for i in 0 to 3 generate
--
attribute INIT : string;
attribute INIT of count_lut : label is "6606";
--
begin
register_bit: FDRE
port map ( D => next_count(i),
Q => pointer(i),
CE => data_present_int,
R => reset,
C => clk);
count_lut: LUT4
--synthesis translate_off
generic map (INIT => X"6606")
--synthesis translate_on
port map( I0 => pointer(i),
I1 => read,
I2 => pointer_zero,
I3 => write,
O => half_count(i));
lsb_count: if i=0 generate
begin
count_muxcy: MUXCY
port map( DI => pointer(i),
CI => valid_write,
S => half_count(i),
O => count_carry(i));
count_xor: XORCY
port map( LI => half_count(i),
CI => valid_write,
O => next_count(i));
end generate lsb_count;
mid_count: if i>0 and i<3 generate
begin
count_muxcy: MUXCY
port map( DI => pointer(i),
CI => count_carry(i-1),
S => half_count(i),
O => count_carry(i));
count_xor: XORCY
port map( LI => half_count(i),
CI => count_carry(i-1),
O => next_count(i));
end generate mid_count;
upper_count: if i=3 generate
begin
count_xor: XORCY
port map( LI => half_count(i),
CI => count_carry(i-1),
O => next_count(i));
end generate upper_count;
end generate count_width_loop;
-- Detect when pointer is zero and maximum
zero_lut: LUT4
--synthesis translate_off
generic map (INIT => X"0001")
--synthesis translate_on
port map( I0 => pointer(0),
I1 => pointer(1),
I2 => pointer(2),
I3 => pointer(3),
O => pointer_zero );
full_lut: LUT4
--synthesis translate_off
generic map (INIT => X"8000")
--synthesis translate_on
port map( I0 => pointer(0),
I1 => pointer(1),
I2 => pointer(2),
I3 => pointer(3),
O => pointer_full );
-- Data Present status
dp_lut: LUT4
--synthesis translate_off
generic map (INIT => X"BFA0")
--synthesis translate_on
port map( I0 => write,
I1 => read,
I2 => pointer_zero,
I3 => data_present_int,
O => decode_data_present );
dp_flop: FDR
port map ( D => decode_data_present,
Q => data_present_int,
R => reset,
C => clk);
-- Valid write signal
valid_lut: LUT3
--synthesis translate_off
generic map (INIT => X"C4")
--synthesis translate_on
port map( I0 => pointer_full,
I1 => write,
I2 => read,
O => valid_write );
-- assign internal signals to outputs
full <= pointer_full;
half_full <= pointer(3);
data_present <= data_present_int;
end low_level_definition;
------------------------------------------------------------------------------------
--
-- END OF FILE BBFIFO_16x8.VHD
--
------------------------------------------------------------------------------------
lib/uart/src/xilinx/kcuart/kcuart_rx.vhd
+352
View File
@@ -0,0 +1,352 @@
-- Constant (K) Compact UART Receiver
--
-- Version : 1.10
-- Version Date : 3rd December 2003
-- Reason : '--translate' directives changed to '--synthesis translate' directives
--
-- Version : 1.00
-- Version Date : 16th October 2002
--
-- Start of design entry : 16th October 2002
--
-- Ken Chapman
-- Xilinx Ltd
-- Benchmark House
-- 203 Brooklands Road
-- Weybridge
-- Surrey KT13 ORH
-- United Kingdom
--
-- chapman@xilinx.com
--
------------------------------------------------------------------------------------
--
-- NOTICE:
--
-- Copyright Xilinx, Inc. 2002. This code may be contain portions patented by other
-- third parties. By providing this core as one possible implementation of a standard,
-- Xilinx is making no representation that the provided implementation of this standard
-- is free from any claims of infringement by any third party. Xilinx expressly
-- disclaims any warranty with respect to the adequacy of the implementation, including
-- but not limited to any warranty or representation that the implementation is free
-- from claims of any third party. Futhermore, Xilinx is providing this core as a
-- courtesy to you and suggests that you contact all third parties to obtain the
-- necessary rights to use this implementation.
--
------------------------------------------------------------------------------------
--
-- Library declarations
--
-- The Unisim Library is used to define Xilinx primitives. It is also used during
-- simulation. The source can be viewed at %XILINX%\vhdl\src\unisims\unisim_VCOMP.vhd
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library unisim;
use unisim.vcomponents.all;
--
------------------------------------------------------------------------------------
--
-- Main Entity for KCUART_RX
--
entity kcuart_rx is
Port ( serial_in : in std_logic;
data_out : out std_logic_vector(7 downto 0);
data_strobe : out std_logic;
en_16_x_baud : in std_logic;
clk : in std_logic);
end kcuart_rx;
--
------------------------------------------------------------------------------------
--
-- Start of Main Architecture for KCUART_RX
--
architecture low_level_definition of kcuart_rx is
--
------------------------------------------------------------------------------------
--
------------------------------------------------------------------------------------
--
-- Signals used in KCUART_RX
--
------------------------------------------------------------------------------------
--
signal sync_serial : std_logic;
signal stop_bit : std_logic;
signal data_int : std_logic_vector(7 downto 0);
signal data_delay : std_logic_vector(7 downto 0);
signal start_delay : std_logic;
signal start_bit : std_logic;
signal edge_delay : std_logic;
signal start_edge : std_logic;
signal decode_valid_char : std_logic;
signal valid_char : std_logic;
signal decode_purge : std_logic;
signal purge : std_logic;
signal valid_srl_delay : std_logic_vector(8 downto 0);
signal valid_reg_delay : std_logic_vector(8 downto 0);
signal decode_data_strobe : std_logic;
--
--
------------------------------------------------------------------------------------
--
-- Attributes to define LUT contents during implementation
-- The information is repeated in the generic map for functional simulation--
--
------------------------------------------------------------------------------------
--
attribute INIT : string;
attribute INIT of start_srl : label is "0000";
attribute INIT of edge_srl : label is "0000";
attribute INIT of valid_lut : label is "0040";
attribute INIT of purge_lut : label is "54";
attribute INIT of strobe_lut : label is "8";
--
------------------------------------------------------------------------------------
--
-- Start of KCUART_RX circuit description
--
------------------------------------------------------------------------------------
--
begin
-- Synchronise input serial data to system clock
sync_reg: FD
port map ( D => serial_in,
Q => sync_serial,
C => clk);
stop_reg: FD
port map ( D => sync_serial,
Q => stop_bit,
C => clk);
-- Data delays to capture data at 16 time baud rate
-- Each SRL16E is followed by a flip-flop for best timing
data_loop: for i in 0 to 7 generate
begin
lsbs: if i<7 generate
--
attribute INIT : string;
attribute INIT of delay15_srl : label is "0000";
--
begin
delay15_srl: SRL16E
--synthesis translate_off
generic map (INIT => X"0000")
--synthesis translate_on
port map( D => data_int(i+1),
CE => en_16_x_baud,
CLK => clk,
A0 => '0',
A1 => '1',
A2 => '1',
A3 => '1',
Q => data_delay(i) );
end generate lsbs;
msb: if i=7 generate
--
attribute INIT : string;
attribute INIT of delay15_srl : label is "0000";
--
begin
delay15_srl: SRL16E
--synthesis translate_off
generic map (INIT => X"0000")
--synthesis translate_on
port map( D => stop_bit,
CE => en_16_x_baud,
CLK => clk,
A0 => '0',
A1 => '1',
A2 => '1',
A3 => '1',
Q => data_delay(i) );
end generate msb;
data_reg: FDE
port map ( D => data_delay(i),
Q => data_int(i),
CE => en_16_x_baud,
C => clk);
end generate data_loop;
-- Assign internal signals to outputs
data_out <= data_int;
-- Data delays to capture start bit at 16 time baud rate
start_srl: SRL16E
--synthesis translate_off
generic map (INIT => X"0000")
--synthesis translate_on
port map( D => data_int(0),
CE => en_16_x_baud,
CLK => clk,
A0 => '0',
A1 => '1',
A2 => '1',
A3 => '1',
Q => start_delay );
start_reg: FDE
port map ( D => start_delay,
Q => start_bit,
CE => en_16_x_baud,
C => clk);
-- Data delays to capture start bit leading edge at 16 time baud rate
-- Delay ensures data is captured at mid-bit position
edge_srl: SRL16E
--synthesis translate_off
generic map (INIT => X"0000")
--synthesis translate_on
port map( D => start_bit,
CE => en_16_x_baud,
CLK => clk,
A0 => '1',
A1 => '0',
A2 => '1',
A3 => '0',
Q => edge_delay );
edge_reg: FDE
port map ( D => edge_delay,
Q => start_edge,
CE => en_16_x_baud,
C => clk);
-- Detect a valid character
valid_lut: LUT4
--synthesis translate_off
generic map (INIT => X"0040")
--synthesis translate_on
port map( I0 => purge,
I1 => stop_bit,
I2 => start_edge,
I3 => edge_delay,
O => decode_valid_char );
valid_reg: FDE
port map ( D => decode_valid_char,
Q => valid_char,
CE => en_16_x_baud,
C => clk);
-- Purge of data status
purge_lut: LUT3
--synthesis translate_off
generic map (INIT => X"54")
--synthesis translate_on
port map( I0 => valid_reg_delay(8),
I1 => valid_char,
I2 => purge,
O => decode_purge );
purge_reg: FDE
port map ( D => decode_purge,
Q => purge,
CE => en_16_x_baud,
C => clk);
-- Delay of valid_char pulse of length equivalent to the time taken
-- to purge data shift register of all data which has been used.
-- Requires 9x16 + 8 delays which is achieved by packing of SRL16E with
-- up to 16 delays and utilising the dedicated flip flop in each stage.
valid_loop: for i in 0 to 8 generate
begin
lsb: if i=0 generate
--
attribute INIT : string;
attribute INIT of delay15_srl : label is "0000";
--
begin
delay15_srl: SRL16E
--synthesis translate_off
generic map (INIT => X"0000")
--synthesis translate_on
port map( D => valid_char,
CE => en_16_x_baud,
CLK => clk,
A0 => '0',
A1 => '1',
A2 => '1',
A3 => '1',
Q => valid_srl_delay(i) );
end generate lsb;
msbs: if i>0 generate
--
attribute INIT : string;
attribute INIT of delay16_srl : label is "0000";
--
begin
delay16_srl: SRL16E
--synthesis translate_off
generic map (INIT => X"0000")
--synthesis translate_on
port map( D => valid_reg_delay(i-1),
CE => en_16_x_baud,
CLK => clk,
A0 => '1',
A1 => '1',
A2 => '1',
A3 => '1',
Q => valid_srl_delay(i) );
end generate msbs;
data_reg: FDE
port map ( D => valid_srl_delay(i),
Q => valid_reg_delay(i),
CE => en_16_x_baud,
C => clk);
end generate valid_loop;
-- Form data strobe
strobe_lut: LUT2
--synthesis translate_off
generic map (INIT => X"8")
--synthesis translate_on
port map( I0 => valid_char,
I1 => en_16_x_baud,
O => decode_data_strobe );
strobe_reg: FD
port map ( D => decode_data_strobe,
Q => data_strobe,
C => clk);
end low_level_definition;
------------------------------------------------------------------------------------
--
-- END OF FILE KCUART_RX.VHD
--
------------------------------------------------------------------------------------
lib/uart/src/xilinx/kcuart/kcuart_tx.vhd
+394
View File
@@ -0,0 +1,394 @@
-- Constant (K) Compact UART Transmitter
--
-- Version : 1.10
-- Version Date : 3rd December 2003
-- Reason : '--translate' directives changed to '--synthesis translate' directives
--
-- Version : 1.00
-- Version Date : 14th October 2002
--
-- Start of design entry : 2nd October 2002
--
-- Ken Chapman
-- Xilinx Ltd
-- Benchmark House
-- 203 Brooklands Road
-- Weybridge
-- Surrey KT13 ORH
-- United Kingdom
--
-- chapman@xilinx.com
--
------------------------------------------------------------------------------------
--
-- NOTICE:
--
-- Copyright Xilinx, Inc. 2002. This code may be contain portions patented by other
-- third parties. By providing this core as one possible implementation of a standard,
-- Xilinx is making no representation that the provided implementation of this standard
-- is free from any claims of infringement by any third party. Xilinx expressly
-- disclaims any warranty with respect to the adequacy of the implementation, including
-- but not limited to any warranty or representation that the implementation is free
-- from claims of any third party. Futhermore, Xilinx is providing this core as a
-- courtesy to you and suggests that you contact all third parties to obtain the
-- necessary rights to use this implementation.
--
------------------------------------------------------------------------------------
--
-- Library declarations
--
-- The Unisim Library is used to define Xilinx primitives. It is also used during
-- simulation. The source can be viewed at %XILINX%\vhdl\src\unisims\unisim_VCOMP.vhd
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library unisim;
use unisim.vcomponents.all;
--
------------------------------------------------------------------------------------
--
-- Main Entity for KCUART_TX
--
entity kcuart_tx is
Port ( data_in : in std_logic_vector(7 downto 0);
send_character : in std_logic;
en_16_x_baud : in std_logic;
serial_out : out std_logic;
Tx_complete : out std_logic;
clk : in std_logic);
end kcuart_tx;
--
------------------------------------------------------------------------------------
--
-- Start of Main Architecture for KCUART_TX
--
architecture low_level_definition of kcuart_tx is
--
------------------------------------------------------------------------------------
--
------------------------------------------------------------------------------------
--
-- Signals used in KCUART_TX
--
------------------------------------------------------------------------------------
--
signal data_01 : std_logic;
signal data_23 : std_logic;
signal data_45 : std_logic;
signal data_67 : std_logic;
signal data_0123 : std_logic;
signal data_4567 : std_logic;
signal data_01234567 : std_logic;
signal bit_select : std_logic_vector(2 downto 0);
signal next_count : std_logic_vector(2 downto 0);
signal mask_count : std_logic_vector(2 downto 0);
signal mask_count_carry : std_logic_vector(2 downto 0);
signal count_carry : std_logic_vector(2 downto 0);
signal ready_to_start : std_logic;
signal decode_Tx_start : std_logic;
signal Tx_start : std_logic;
signal decode_Tx_run : std_logic;
signal Tx_run : std_logic;
signal decode_hot_state : std_logic;
signal hot_state : std_logic;
signal hot_delay : std_logic;
signal Tx_bit : std_logic;
signal decode_Tx_stop : std_logic;
signal Tx_stop : std_logic;
signal decode_Tx_complete : std_logic;
--
--
------------------------------------------------------------------------------------
--
-- Attributes to define LUT contents during implementation
-- The information is repeated in the generic map for functional simulation--
--
------------------------------------------------------------------------------------
--
attribute INIT : string;
attribute INIT of mux1_lut : label is "E4FF";
attribute INIT of mux2_lut : label is "E4FF";
attribute INIT of mux3_lut : label is "E4FF";
attribute INIT of mux4_lut : label is "E4FF";
attribute INIT of ready_lut : label is "10";
attribute INIT of start_lut : label is "0190";
attribute INIT of run_lut : label is "1540";
attribute INIT of hot_state_lut : label is "94";
attribute INIT of delay14_srl : label is "0000";
attribute INIT of stop_lut : label is "0180";
attribute INIT of complete_lut : label is "8";
--
------------------------------------------------------------------------------------
--
-- Start of KCUART_TX circuit description
--
------------------------------------------------------------------------------------
--
begin
-- 8 to 1 multiplexer to convert parallel data to serial
mux1_lut: LUT4
--synthesis translate_off
generic map (INIT => X"E4FF")
--synthesis translate_on
port map( I0 => bit_select(0),
I1 => data_in(0),
I2 => data_in(1),
I3 => Tx_run,
O => data_01 );
mux2_lut: LUT4
--synthesis translate_off
generic map (INIT => X"E4FF")
--synthesis translate_on
port map( I0 => bit_select(0),
I1 => data_in(2),
I2 => data_in(3),
I3 => Tx_run,
O => data_23 );
mux3_lut: LUT4
--synthesis translate_off
generic map (INIT => X"E4FF")
--synthesis translate_on
port map( I0 => bit_select(0),
I1 => data_in(4),
I2 => data_in(5),
I3 => Tx_run,
O => data_45 );
mux4_lut: LUT4
--synthesis translate_off
generic map (INIT => X"E4FF")
--synthesis translate_on
port map( I0 => bit_select(0),
I1 => data_in(6),
I2 => data_in(7),
I3 => Tx_run,
O => data_67 );
mux5_muxf5: MUXF5
port map( I1 => data_23,
I0 => data_01,
S => bit_select(1),
O => data_0123 );
mux6_muxf5: MUXF5
port map( I1 => data_67,
I0 => data_45,
S => bit_select(1),
O => data_4567 );
mux7_muxf6: MUXF6
port map( I1 => data_4567,
I0 => data_0123,
S => bit_select(2),
O => data_01234567 );
-- Register serial output and force start and stop bits
pipeline_serial: FDRS
port map ( D => data_01234567,
Q => serial_out,
R => Tx_start,
S => Tx_stop,
C => clk);
-- 3-bit counter
-- Counter is clock enabled by en_16_x_baud
-- Counter will be reset when 'Tx_start' is active
-- Counter will increment when Tx_bit is active
-- Tx_run must be active to count
-- count_carry(2) indicates when terminal count (7) is reached and Tx_bit=1 (ie overflow)
count_width_loop: for i in 0 to 2 generate
--
attribute INIT : string;
attribute INIT of count_lut : label is "8";
--
begin
register_bit: FDRE
port map ( D => next_count(i),
Q => bit_select(i),
CE => en_16_x_baud,
R => Tx_start,
C => clk);
count_lut: LUT2
--synthesis translate_off
generic map (INIT => X"8")
--synthesis translate_on
port map( I0 => bit_select(i),
I1 => Tx_run,
O => mask_count(i));
mask_and: MULT_AND
port map( I0 => bit_select(i),
I1 => Tx_run,
LO => mask_count_carry(i));
lsb_count: if i=0 generate
begin
count_muxcy: MUXCY
port map( DI => mask_count_carry(i),
CI => Tx_bit,
S => mask_count(i),
O => count_carry(i));
count_xor: XORCY
port map( LI => mask_count(i),
CI => Tx_bit,
O => next_count(i));
end generate lsb_count;
upper_count: if i>0 generate
begin
count_muxcy: MUXCY
port map( DI => mask_count_carry(i),
CI => count_carry(i-1),
S => mask_count(i),
O => count_carry(i));
count_xor: XORCY
port map( LI => mask_count(i),
CI => count_carry(i-1),
O => next_count(i));
end generate upper_count;
end generate count_width_loop;
-- Ready to start decode
ready_lut: LUT3
--synthesis translate_off
generic map (INIT => X"10")
--synthesis translate_on
port map( I0 => Tx_run,
I1 => Tx_start,
I2 => send_character,
O => ready_to_start );
-- Start bit enable
start_lut: LUT4
--synthesis translate_off
generic map (INIT => X"0190")
--synthesis translate_on
port map( I0 => Tx_bit,
I1 => Tx_stop,
I2 => ready_to_start,
I3 => Tx_start,
O => decode_Tx_start );
Tx_start_reg: FDE
port map ( D => decode_Tx_start,
Q => Tx_start,
CE => en_16_x_baud,
C => clk);
-- Run bit enable
run_lut: LUT4
--synthesis translate_off
generic map (INIT => X"1540")
--synthesis translate_on
port map( I0 => count_carry(2),
I1 => Tx_bit,
I2 => Tx_start,
I3 => Tx_run,
O => decode_Tx_run );
Tx_run_reg: FDE
port map ( D => decode_Tx_run,
Q => Tx_run,
CE => en_16_x_baud,
C => clk);
-- Bit rate enable
hot_state_lut: LUT3
--synthesis translate_off
generic map (INIT => X"94")
--synthesis translate_on
port map( I0 => Tx_stop,
I1 => ready_to_start,
I2 => Tx_bit,
O => decode_hot_state );
hot_state_reg: FDE
port map ( D => decode_hot_state,
Q => hot_state,
CE => en_16_x_baud,
C => clk);
delay14_srl: SRL16E
--synthesis translate_off
generic map (INIT => X"0000")
--synthesis translate_on
port map( D => hot_state,
CE => en_16_x_baud,
CLK => clk,
A0 => '1',
A1 => '0',
A2 => '1',
A3 => '1',
Q => hot_delay );
Tx_bit_reg: FDE
port map ( D => hot_delay,
Q => Tx_bit,
CE => en_16_x_baud,
C => clk);
-- Stop bit enable
stop_lut: LUT4
--synthesis translate_off
generic map (INIT => X"0180")
--synthesis translate_on
port map( I0 => Tx_bit,
I1 => Tx_run,
I2 => count_carry(2),
I3 => Tx_stop,
O => decode_Tx_stop );
Tx_stop_reg: FDE
port map ( D => decode_Tx_stop,
Q => Tx_stop,
CE => en_16_x_baud,
C => clk);
-- Tx_complete strobe
complete_lut: LUT2
--synthesis translate_off
generic map (INIT => X"8")
--synthesis translate_on
port map( I0 => count_carry(2),
I1 => en_16_x_baud,
O => decode_Tx_complete );
Tx_complete_reg: FD
port map ( D => decode_Tx_complete,
Q => Tx_complete,
C => clk);
end low_level_definition;
------------------------------------------------------------------------------------
--
-- END OF FILE KCUART_TX.VHD
--
------------------------------------------------------------------------------------
lib/uart/src/xilinx/uart.vhd
+103
View File
@@ -0,0 +1,103 @@
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
LIBRARY WORK;
USE WORK.uart_types.all;
------------------------------------------------------------------------------------
ENTITY uart IS
Port
(
clk : in STD_LOGIC;
rst : in STD_LOGIC;
we : in STD_LOGIC;
re : in STD_LOGIC;
din : in unsigned(7 downto 0);
dout : out unsigned(7 downto 0);
ser_rx : in std_logic;
ser_tx : out std_logic;
ctrl : in ctrl_t;
status : out status_t
);
END uart;
ARCHITECTURE rtl OF uart IS
signal baud_count : unsigned(15 downto 0);
signal en_16_x_baud : std_logic;
signal rx_data_present : std_logic;
signal rx_full : std_logic;
signal rx_half_full : std_logic;
signal tx_complete : std_logic;
signal tx_empty : std_logic;
signal tx_full : std_logic;
signal tx_half_full : std_logic;
signal data_out : std_logic_vector(7 downto 0);
begin
dout <= unsigned(data_out);
baud_timer:
process(clk)
begin
if rising_edge(clk) then
en_16_x_baud <= '0';
if rst = '1' then
baud_count <= (others => '0');
elsif baud_count = ctrl.baudrate then
baud_count <= (others => '0');
en_16_x_baud <= '1';
else
baud_count <= baud_count + 1;
end if;
end if;
end process;
inst_uart_tx: entity work.uart_tx
port map
(
data_in => std_logic_vector(din),
write_buffer => we,
reset_buffer => rst,
en_16_x_baud => en_16_x_baud,
serial_out => ser_tx,
buffer_full => tx_full,
buffer_half_full => tx_half_full,
tx_complete => tx_complete,
tx_empty => tx_empty,
clk => clk
);
inst_uart_rx: entity work.uart_rx
port map
(
serial_in => ser_rx,
data_out => data_out,
read_buffer => re,
reset_buffer => rst,
en_16_x_baud => en_16_x_baud,
buffer_data_present => rx_data_present,
buffer_full => rx_full,
buffer_half_full => rx_half_full,
clk => clk
);
-- Status
status.rx_present <= rx_data_present;
status.tx_complete <= tx_complete;
status.tx_empty <= tx_empty;
status.tx_full <= tx_full;
end rtl;
------------------------------------------------------------------------------------
--
-- END OF FILE UART_RX.VHD
--
------------------------------------------------------------------------------------
lib/uart/src/xilinx/uart_rx.vhd
+145
View File
@@ -0,0 +1,145 @@
-- UART Receiver with integral 16 byte FIFO buffer
--
-- 8 bit, no parity, 1 stop bit
--
-- Version : 1.00
-- Version Date : 16th October 2002
--
-- Start of design entry : 16th October 2002
--
-- Ken Chapman
-- Xilinx Ltd
-- Benchmark House
-- 203 Brooklands Road
-- Weybridge
-- Surrey KT13 ORH
-- United Kingdom
--
-- chapman@xilinx.com
--
------------------------------------------------------------------------------------
--
-- NOTICE:
--
-- Copyright Xilinx, Inc. 2002. This code may be contain portions patented by other
-- third parties. By providing this core as one possible implementation of a standard,
-- Xilinx is making no representation that the provided implementation of this standard
-- is free from any claims of infringement by any third party. Xilinx expressly
-- disclaims any warranty with respect to the adequacy of the implementation, including
-- but not limited to any warranty or representation that the implementation is free
-- from claims of any third party. Futhermore, Xilinx is providing this core as a
-- courtesy to you and suggests that you contact all third parties to obtain the
-- necessary rights to use this implementation.
--
------------------------------------------------------------------------------------
--
-- Library declarations
--
-- The Unisim Library is used to define Xilinx primitives. It is also used during
-- simulation. The source can be viewed at %XILINX%\vhdl\src\unisims\unisim_VCOMP.vhd
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library unisim;
use unisim.vcomponents.all;
--
------------------------------------------------------------------------------------
--
-- Main Entity for UART_RX
--
entity uart_rx is
Port ( serial_in : in std_logic;
data_out : out std_logic_vector(7 downto 0);
read_buffer : in std_logic;
reset_buffer : in std_logic;
en_16_x_baud : in std_logic;
buffer_data_present : out std_logic;
buffer_full : out std_logic;
buffer_half_full : out std_logic;
clk : in std_logic);
end uart_rx;
--
------------------------------------------------------------------------------------
--
-- Start of Main Architecture for UART_RX
--
architecture macro_level_definition of uart_rx is
--
------------------------------------------------------------------------------------
--
-- Components used in UART_RX and defined in subsequent entities.
--
------------------------------------------------------------------------------------
--
-- Constant (K) Compact UART Receiver
--
component kcuart_rx
Port ( serial_in : in std_logic;
data_out : out std_logic_vector(7 downto 0);
data_strobe : out std_logic;
en_16_x_baud : in std_logic;
clk : in std_logic);
end component;
--
-- 'Bucket Brigade' FIFO
--
component bbfifo_16x8
Port ( data_in : in std_logic_vector(7 downto 0);
data_out : out std_logic_vector(7 downto 0);
reset : in std_logic;
write : in std_logic;
read : in std_logic;
full : out std_logic;
half_full : out std_logic;
data_present : out std_logic;
clk : in std_logic);
end component;
--
------------------------------------------------------------------------------------
--
-- Signals used in UART_RX
--
------------------------------------------------------------------------------------
--
signal uart_data_out : std_logic_vector(7 downto 0);
signal fifo_write : std_logic;
--
------------------------------------------------------------------------------------
--
-- Start of UART_RX circuit description
--
------------------------------------------------------------------------------------
--
begin
-- 8 to 1 multiplexer to convert parallel data to serial
kcuart: kcuart_rx
port map ( serial_in => serial_in,
data_out => uart_data_out,
data_strobe => fifo_write,
en_16_x_baud => en_16_x_baud,
clk => clk );
buf: bbfifo_16x8
port map ( data_in => uart_data_out,
data_out => data_out,
reset => reset_buffer,
write => fifo_write,
read => read_buffer,
full => buffer_full,
half_full => buffer_half_full,
data_present => buffer_data_present,
clk => clk);
end macro_level_definition;
------------------------------------------------------------------------------------
--
-- END OF FILE UART_RX.VHD
--
------------------------------------------------------------------------------------
lib/uart/src/xilinx/uart_tx.vhd
+152
View File
@@ -0,0 +1,152 @@
-- UART Transmitter with integral 16 byte FIFO buffer
--
-- 8 bit, no parity, 1 stop bit
--
-- Version : 1.00
-- Version Date : 14th October 2002
--
-- Start of design entry : 14th October 2002
--
-- Ken Chapman
-- Xilinx Ltd
-- Benchmark House
-- 203 Brooklands Road
-- Weybridge
-- Surrey KT13 ORH
-- United Kingdom
--
-- chapman@xilinx.com
--
------------------------------------------------------------------------------------
--
-- NOTICE:
--
-- Copyright Xilinx, Inc. 2002. This code may be contain portions patented by other
-- third parties. By providing this core as one possible implementation of a standard,
-- Xilinx is making no representation that the provided implementation of this standard
-- is free from any claims of infringement by any third party. Xilinx expressly
-- disclaims any warranty with respect to the adequacy of the implementation, including
-- but not limited to any warranty or representation that the implementation is free
-- from claims of any third party. Futhermore, Xilinx is providing this core as a
-- courtesy to you and suggests that you contact all third parties to obtain the
-- necessary rights to use this implementation.
--
------------------------------------------------------------------------------------
--
-- Library declarations
--
-- The Unisim Library is used to define Xilinx primitives. It is also used during
-- simulation. The source can be viewed at %XILINX%\vhdl\src\unisims\unisim_VCOMP.vhd
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library unisim;
use unisim.vcomponents.all;
--
------------------------------------------------------------------------------------
--
-- Main Entity for UART_TX
--
entity uart_tx is
Port ( data_in : in std_logic_vector(7 downto 0);
write_buffer : in std_logic;
reset_buffer : in std_logic;
en_16_x_baud : in std_logic;
serial_out : out std_logic;
buffer_full : out std_logic;
buffer_half_full : out std_logic;
tx_complete : out std_logic;
tx_empty : out std_logic;
clk : in std_logic);
end uart_tx;
--
------------------------------------------------------------------------------------
--
-- Start of Main Architecture for UART_TX
--
architecture macro_level_definition of uart_tx is
--
------------------------------------------------------------------------------------
--
-- Components used in UART_TX and defined in subsequent entities.
--
------------------------------------------------------------------------------------
--
-- Constant (K) Compact UART Transmitter
--
component kcuart_tx
Port ( data_in : in std_logic_vector(7 downto 0);
send_character : in std_logic;
en_16_x_baud : in std_logic;
serial_out : out std_logic;
Tx_complete : out std_logic;
clk : in std_logic);
end component;
--
-- 'Bucket Brigade' FIFO
--
component bbfifo_16x8
Port ( data_in : in std_logic_vector(7 downto 0);
data_out : out std_logic_vector(7 downto 0);
reset : in std_logic;
write : in std_logic;
read : in std_logic;
full : out std_logic;
half_full : out std_logic;
data_present : out std_logic;
clk : in std_logic);
end component;
--
------------------------------------------------------------------------------------
--
-- Signals used in UART_TX
--
------------------------------------------------------------------------------------
--
signal fifo_data_out : std_logic_vector(7 downto 0);
signal fifo_data_present : std_logic;
signal fifo_read : std_logic;
--
------------------------------------------------------------------------------------
--
-- Start of UART_TX circuit description
--
------------------------------------------------------------------------------------
--
begin
tx_complete <= fifo_read;
tx_empty <= not fifo_data_present;
-- 8 to 1 multiplexer to convert parallel data to serial
kcuart: kcuart_tx
port map ( data_in => fifo_data_out,
send_character => fifo_data_present,
en_16_x_baud => en_16_x_baud,
serial_out => serial_out,
Tx_complete => fifo_read,
clk => clk);
buf: bbfifo_16x8
port map ( data_in => data_in,
data_out => fifo_data_out,
reset => reset_buffer,
write => write_buffer,
read => fifo_read,
full => buffer_full,
half_full => buffer_half_full,
data_present => fifo_data_present,
clk => clk);
end macro_level_definition;
------------------------------------------------------------------------------------
--
-- END OF FILE UART_TX.VHD
--
------------------------------------------------------------------------------------