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- added clock divider

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- fixed clock edge of Slave TX

git-svn-id: http://moon:8086/svn/vhdl/trunk@1280 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
jens
2015-06-04 12:17:00 +00:00
parent 8097a4f41c
commit d1407db11d
4 changed files with 86 additions and 32 deletions
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lib/spi/src/tb_spi_master.vhd
+27 -15
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@@ -60,12 +60,14 @@ ARCHITECTURE behavior OF tb_spi_master IS
signal slv_tx_shiftreg : unsigned(31 downto 0) := (others => '0');
signal slv_rx_valid_pipe : unsigned(31 downto 0) := (others => '0');
signal slv_rx_data : unsigned(31 downto 0) := (others => '0');
signal slv_rx_data_vld : STD_LOGIC;
BEGIN
ctrl.cpol <= '0';
ctrl.cpha <= '0';
ctrl.msb_first <= '1';
ctrl.clk_div <= X"00";
inst_spi_master : entity work.spi_master
GENERIC MAP
@@ -104,16 +106,26 @@ CLK_GEN: process
RX_SLAVE_SIM_SHIFT_REG: process(mst_clk)
begin
if rising_edge(mst_clk) then
slv_rx_data_vld <= '0';
if mso = '1' then
if slv_rx_valid_pipe(slv_rx_valid_pipe'left) = '1' then
slv_rx_valid_pipe <= (slv_rx_valid_pipe'left downto 1 => '0') & '1';
slv_rx_data_vld <= '1';
else
slv_rx_valid_pipe <= slv_rx_valid_pipe(slv_rx_valid_pipe'left-1 downto 0) & '1';
end if;
slv_rx_shiftreg <= slv_rx_shiftreg(slv_rx_shiftreg'left-1 downto 0) & mosi;
slv_tx_shiftreg <= slv_tx_shiftreg(slv_tx_shiftreg'left-1 downto 0) & mosi;
end if;
end if;
end process;
TX_SLAVE_SIM_SHIFT_REG: process(mst_clk)
begin
if falling_edge(mst_clk) then
if slv_rx_data_vld = '1' then
slv_tx_shiftreg <= slv_rx_shiftreg;
else
slv_tx_shiftreg <= slv_tx_shiftreg(slv_tx_shiftreg'left-1 downto 0) & mosi;
slv_tx_shiftreg <= slv_tx_shiftreg(slv_tx_shiftreg'left-1 downto 0) & '0';
end if;
end if;
end process;
@@ -186,19 +198,6 @@ STIMULUS: process
wait until rising_edge(CLK) and mst_din_rdy = '1';
mst_din_vld <= '0';
--------------------------------------------------------
wait until rising_edge(CLK);
mst_din <= X"C355AAC1";
mst_din_vld <= '1';
wait until rising_edge(CLK) and mst_din_rdy = '1';
mst_din_vld <= '0';
wait until rising_edge(CLK);
mst_cmd <= to_cmd(64, 32);
mst_cmd_vld <= '1';
wait until rising_edge(CLK) and mst_cmd_rdy = '1';
mst_cmd_vld <= '0';
--------------------------------------------------------
mst_din <= X"00000000";
for i in 0 to 16 loop
@@ -219,6 +218,19 @@ STIMULUS: process
wait until rising_edge(CLK) and mso = '0';
end loop;
--------------------------------------------------------
wait until rising_edge(CLK);
mst_din <= X"C355AAC1";
mst_din_vld <= '1';
wait until rising_edge(CLK) and mst_din_rdy = '1';
mst_din_vld <= '0';
wait until rising_edge(CLK);
mst_cmd <= to_cmd(64, 32);
mst_cmd_vld <= '1';
wait until rising_edge(CLK) and mst_cmd_rdy = '1';
mst_cmd_vld <= '0';
--------------------------------------------------------
wait until rising_edge(CLK);
mst_din <= X"C355AA00";