- added clock divider

- fixed clock edge of Slave TX

git-svn-id: http://moon:8086/svn/vhdl/trunk@1280 cc03376c-175c-47c8-b038-4cd826a8556b

lib/spi/src/spi_master.vhd

@@ -52,7 +52,8 @@ ARCHITECTURE behavior OF spi_master IS
 	signal spi_clk					: std_logic := '0';
 	signal spi_clk_out				: std_logic;
 	signal clk_en					: std_logic;
-	signal spi_clk_data				: std_logic;
+	signal spi_clk_write			: std_logic;
+	signal spi_clk_read				: std_logic;
 	signal spi_rst_count			: unsigned(5 downto 0);
 	signal spi_rst					: std_logic;
 
@@ -81,6 +82,9 @@ ARCHITECTURE behavior OF spi_master IS
 	signal rx_enable				: std_logic;
 	signal slv_enable				: std_logic;
 	
+	signal spi_clk_div_en			: std_logic;
+	signal spi_clk_div_count		: unsigned(7 downto 0);
+
 --------------------------------------------------------------------------
 begin
 
@@ -89,7 +93,8 @@ begin
 	write_fifo_din			<= din;
 	cmd_reg 				<= to_cmd(cat_fifo_dout);
 	mosi					<= tx_shift_reg(tx_shift_reg'left) when ctrl_reg.msb_first = '1' else tx_shift_reg(tx_shift_reg'right);
-	spi_clk_data			<= spi_clk xor ctrl_reg.cpha;
+	spi_clk_write			<= spi_clk xor ctrl_reg.cpha;
+	spi_clk_read			<= spi_clk_out;
 	
 	dout_vld				<= not read_fifo_empty;
 	status.cmd_fifo_full	<= cat_fifo_full;
@@ -170,16 +175,14 @@ begin
 	);
 
 --------------------------------------------------------------------------
-proc_spi_clk_gen:
+proc_spi_rst_gen:
 process(clk)
 begin
 	if rising_edge(clk) then
 		if rst = '1' then
 			spi_rst <= '1';
-			spi_clk	<= '0';
 			spi_rst_count	<= (others => '1');
 		else
-			spi_clk	<= not spi_clk;
 			if spi_rst_count /= to_unsigned(0, spi_rst_count'length) then
 				spi_rst_count	<= spi_rst_count - 1;
 			else
@@ -189,16 +192,46 @@ begin
 	end if;
 end process;
 
+proc_spi_clk_divider:
+process(clk)
+begin
+	if rising_edge(clk) then
+		spi_clk_div_en <= '0';
+		if rst = '1' then
+			spi_clk_div_count <= (others => '0');
+		elsif spi_clk_div_count = ctrl.clk_div then
+			spi_clk_div_count	<= (others => '0');
+			spi_clk_div_en		<= '1';
+		else
+			spi_clk_div_count <= spi_clk_div_count + 1;
+		end if;
+	end if;
+end process;
+
+proc_spi_clk_gen:
+process(clk)
+begin
+	if rising_edge(clk) then
+		if rst = '1' then
+			spi_clk	<= '0';
+		elsif spi_clk_div_en = '1' then
+			spi_clk	<= not spi_clk;
+		end if ;
+	end if;
+end process;
+
 proc_spi_clk_out_gen:
 process(clk)
 begin
 	if rising_edge(clk) then
 		if spi_rst = '1' then
 			spi_clk_out	<= '0';
-		elsif clk_en = '0' then
-			spi_clk_out	<= ctrl_reg.cpol;
-		else
-			spi_clk_out	<= not spi_clk_out;
+		elsif spi_clk_div_en = '1' then	
+			if clk_en = '0' then
+				spi_clk_out	<= ctrl_reg.cpol;
+			else
+				spi_clk_out	<= not spi_clk_out;
+			end if;
 		end if;
 	end if;
 end process;
@@ -338,9 +371,9 @@ begin
 end process;
 
 PROC_TX_SHIFT_REG:
-process(spi_clk_data)
+process(spi_clk_write)
 begin
-	if rising_edge(spi_clk_data) then
+	if rising_edge(spi_clk_write) then
 		if data_load_en = '1' then
 			tx_shift_reg		<= write_fifo_dout;
 		elsif shift_en = '1' and xfer_count_en = '1' then
@@ -355,9 +388,9 @@ end process;
 
 -- Receiver
 PROC_RX_SHIFT_REG:
-process(spi_clk_out)
+process(spi_clk_read)
 	begin
-		if rising_edge(spi_clk_out) then
+		if rising_edge(spi_clk_read) then
 			if shift_en = '1' and xfer_count_en = '1' then
 				if slv_enable = '1' then
 					if (ctrl_reg.msb_first = '1') then