diff --git a/lib/SDRAM/ddr_sdr_v1_5/sim/tb_ctrl_sdr_wb32.fdo b/lib/SDRAM/ddr_sdr_v1_5/sim/tb_ctrl_sdr_wb32.fdo index e0dcfb1..c649a16 100644 --- a/lib/SDRAM/ddr_sdr_v1_5/sim/tb_ctrl_sdr_wb32.fdo +++ b/lib/SDRAM/ddr_sdr_v1_5/sim/tb_ctrl_sdr_wb32.fdo @@ -30,4 +30,4 @@ do {tb_ctrl_sdr_wb32.wdo} view wave view structure view signals -run 200us +run 120us diff --git a/lib/SDRAM/ddr_sdr_v1_5/sim/tb_ctrl_sdr_wb32.wdo b/lib/SDRAM/ddr_sdr_v1_5/sim/tb_ctrl_sdr_wb32.wdo index 7908093..02c83e3 100644 --- a/lib/SDRAM/ddr_sdr_v1_5/sim/tb_ctrl_sdr_wb32.wdo +++ b/lib/SDRAM/ddr_sdr_v1_5/sim/tb_ctrl_sdr_wb32.wdo @@ -29,6 +29,7 @@ add wave -noupdate -format Logic /tb_ctrl_sdr_wb32/part_ras_n add wave -noupdate -format Logic /tb_ctrl_sdr_wb32/part_cas_n add wave -noupdate -format Literal /tb_ctrl_sdr_wb32/part_ba add wave -noupdate -format Literal /tb_ctrl_sdr_wb32/part_dqm +add wave -noupdate -format Literal /tb_ctrl_sdr_wb32/sd_cmd add wave -noupdate -format Literal -radix hexadecimal /tb_ctrl_sdr_wb32/part_addr add wave -noupdate -format Literal -radix hexadecimal /tb_ctrl_sdr_wb32/part_data add wave -noupdate -divider PHY @@ -61,10 +62,13 @@ add wave -noupdate -format Logic /tb_ctrl_sdr_wb32/uut/inst_sdram_phy/rst0 add wave -noupdate -format Logic /tb_ctrl_sdr_wb32/uut/inst_sdram_phy/locked add wave -noupdate -format Logic /tb_ctrl_sdr_wb32/uut/inst_sdram_phy/error add wave -noupdate -format Literal /tb_ctrl_sdr_wb32/uut/inst_sdram_phy/u_tag_pipe -add wave -noupdate -divider {SDRAM Cmd FSM} +add wave -noupdate -divider {CMD FSM} add wave -noupdate -format Literal /tb_ctrl_sdr_wb32/uut/sdram_ctrl_frontend_wb16/inst_sdram_ctrl_top/inst_sdram_cmd/f_sdrclk add wave -noupdate -format Logic /tb_ctrl_sdr_wb32/uut/sdram_ctrl_frontend_wb16/inst_sdram_ctrl_top/inst_sdram_cmd/rst add wave -noupdate -format Logic /tb_ctrl_sdr_wb32/uut/sdram_ctrl_frontend_wb16/inst_sdram_ctrl_top/inst_sdram_cmd/clk +add wave -noupdate -format Literal /tb_ctrl_sdr_wb32/sd_cmd +add wave -noupdate -format Literal -radix hexadecimal /tb_ctrl_sdr_wb32/part_addr +add wave -noupdate -format Literal -radix hexadecimal /tb_ctrl_sdr_wb32/part_data add wave -noupdate -format Logic /tb_ctrl_sdr_wb32/uut/sdram_ctrl_frontend_wb16/inst_sdram_ctrl_top/inst_sdram_cmd/enable add wave -noupdate -format Literal /tb_ctrl_sdr_wb32/uut/sdram_ctrl_frontend_wb16/inst_sdram_ctrl_top/inst_sdram_cmd/tag add wave -noupdate -format Literal /tb_ctrl_sdr_wb32/uut/sdram_ctrl_frontend_wb16/inst_sdram_ctrl_top/inst_sdram_cmd/col_addr @@ -72,7 +76,7 @@ add wave -noupdate -format Literal /tb_ctrl_sdr_wb32/uut/sdram_ctrl_frontend_wb1 add wave -noupdate -format Literal /tb_ctrl_sdr_wb32/uut/sdram_ctrl_frontend_wb16/inst_sdram_ctrl_top/inst_sdram_cmd/cmd add wave -noupdate -format Logic /tb_ctrl_sdr_wb32/uut/sdram_ctrl_frontend_wb16/inst_sdram_ctrl_top/inst_sdram_cmd/cmd_we add wave -noupdate -format Logic /tb_ctrl_sdr_wb32/uut/sdram_ctrl_frontend_wb16/inst_sdram_ctrl_top/inst_sdram_cmd/cmd_ack -add wave -noupdate -format Literal /tb_ctrl_sdr_wb32/uut/sdram_ctrl_frontend_wb16/inst_sdram_ctrl_top/inst_sdram_cmd/phy_ctrl +add wave -noupdate -format Literal -expand /tb_ctrl_sdr_wb32/uut/sdram_ctrl_frontend_wb16/inst_sdram_ctrl_top/inst_sdram_cmd/phy_ctrl add wave -noupdate -format Literal /tb_ctrl_sdr_wb32/uut/sdram_ctrl_frontend_wb16/inst_sdram_ctrl_top/inst_sdram_cmd/st_sdr add wave -noupdate -format Literal /tb_ctrl_sdr_wb32/uut/sdram_ctrl_frontend_wb16/inst_sdram_ctrl_top/inst_sdram_cmd/st_sdr_next add wave -noupdate -format Literal /tb_ctrl_sdr_wb32/uut/sdram_ctrl_frontend_wb16/inst_sdram_ctrl_top/inst_sdram_cmd/cc_preset @@ -80,8 +84,55 @@ add wave -noupdate -format Logic /tb_ctrl_sdr_wb32/uut/sdram_ctrl_frontend_wb16/ add wave -noupdate -format Logic /tb_ctrl_sdr_wb32/uut/sdram_ctrl_frontend_wb16/inst_sdram_ctrl_top/inst_sdram_cmd/cycle_finished add wave -noupdate -format Logic /tb_ctrl_sdr_wb32/uut/sdram_ctrl_frontend_wb16/inst_sdram_ctrl_top/inst_sdram_cmd/burst_load_en add wave -noupdate -format Logic /tb_ctrl_sdr_wb32/uut/sdram_ctrl_frontend_wb16/inst_sdram_ctrl_top/inst_sdram_cmd/burst_finished +add wave -noupdate -format Literal /tb_ctrl_sdr_wb32/uut/sdram_ctrl_frontend_wb16/inst_sdram_ctrl_top/inst_sdram_cmd/burst_cnt +add wave -noupdate -divider {Main FSM} +add wave -noupdate -format Literal /tb_ctrl_sdr_wb32/uut/sdram_ctrl_frontend_wb16/inst_sdram_ctrl_top/inst_sdram_ctrl/f_sysclk +add wave -noupdate -format Logic /tb_ctrl_sdr_wb32/uut/sdram_ctrl_frontend_wb16/inst_sdram_ctrl_top/inst_sdram_ctrl/rst +add wave -noupdate -format Logic /tb_ctrl_sdr_wb32/uut/sdram_ctrl_frontend_wb16/inst_sdram_ctrl_top/inst_sdram_ctrl/clk +add wave -noupdate -format Logic /tb_ctrl_sdr_wb32/uut/sdram_ctrl_frontend_wb16/inst_sdram_ctrl_top/inst_sdram_ctrl/u_busy +add wave -noupdate -format Literal /tb_ctrl_sdr_wb32/uut/sdram_ctrl_frontend_wb16/inst_sdram_ctrl_top/inst_sdram_ctrl/u_tag_in +add wave -noupdate -format Literal /tb_ctrl_sdr_wb32/uut/sdram_ctrl_frontend_wb16/inst_sdram_ctrl_top/inst_sdram_ctrl/u_tag_out +add wave -noupdate -format Literal /tb_ctrl_sdr_wb32/uut/sdram_ctrl_frontend_wb16/inst_sdram_ctrl_top/inst_sdram_ctrl/u_addr +add wave -noupdate -format Literal /tb_ctrl_sdr_wb32/uut/sdram_ctrl_frontend_wb16/inst_sdram_ctrl_top/inst_sdram_ctrl/u_cmd +add wave -noupdate -format Logic /tb_ctrl_sdr_wb32/uut/sdram_ctrl_frontend_wb16/inst_sdram_ctrl_top/inst_sdram_ctrl/u_cmd_we +add wave -noupdate -format Literal /tb_ctrl_sdr_wb32/uut/sdram_ctrl_frontend_wb16/inst_sdram_ctrl_top/inst_sdram_ctrl/col_addr +add wave -noupdate -format Logic /tb_ctrl_sdr_wb32/uut/sdram_ctrl_frontend_wb16/inst_sdram_ctrl_top/inst_sdram_ctrl/sdr_cmd_busy +add wave -noupdate -format Literal /tb_ctrl_sdr_wb32/uut/sdram_ctrl_frontend_wb16/inst_sdram_ctrl_top/inst_sdram_ctrl/sdr_cmd +add wave -noupdate -format Logic /tb_ctrl_sdr_wb32/uut/sdram_ctrl_frontend_wb16/inst_sdram_ctrl_top/inst_sdram_ctrl/sdr_cmd_we +add wave -noupdate -format Literal /tb_ctrl_sdr_wb32/uut/sdram_ctrl_frontend_wb16/inst_sdram_ctrl_top/inst_sdram_ctrl/sdr_mode +add wave -noupdate -format Logic /tb_ctrl_sdr_wb32/uut/sdram_ctrl_frontend_wb16/inst_sdram_ctrl_top/inst_sdram_ctrl/sdr_cke +add wave -noupdate -format Literal /tb_ctrl_sdr_wb32/uut/sdram_ctrl_frontend_wb16/inst_sdram_ctrl_top/inst_sdram_ctrl/st_ctrl +add wave -noupdate -format Literal /tb_ctrl_sdr_wb32/uut/sdram_ctrl_frontend_wb16/inst_sdram_ctrl_top/inst_sdram_ctrl/st_ctrl_next +add wave -noupdate -format Literal /tb_ctrl_sdr_wb32/uut/sdram_ctrl_frontend_wb16/inst_sdram_ctrl_top/inst_sdram_ctrl/pwr_up_cnt +add wave -noupdate -format Logic /tb_ctrl_sdr_wb32/uut/sdram_ctrl_frontend_wb16/inst_sdram_ctrl_top/inst_sdram_ctrl/pwr_up_cnt_rst +add wave -noupdate -format Logic /tb_ctrl_sdr_wb32/uut/sdram_ctrl_frontend_wb16/inst_sdram_ctrl_top/inst_sdram_ctrl/pwr_up_finished +add wave -noupdate -format Literal /tb_ctrl_sdr_wb32/uut/sdram_ctrl_frontend_wb16/inst_sdram_ctrl_top/inst_sdram_ctrl/cycle_cnt +add wave -noupdate -format Literal /tb_ctrl_sdr_wb32/uut/sdram_ctrl_frontend_wb16/inst_sdram_ctrl_top/inst_sdram_ctrl/cc_preset +add wave -noupdate -format Logic /tb_ctrl_sdr_wb32/uut/sdram_ctrl_frontend_wb16/inst_sdram_ctrl_top/inst_sdram_ctrl/cc_load_en +add wave -noupdate -format Logic /tb_ctrl_sdr_wb32/uut/sdram_ctrl_frontend_wb16/inst_sdram_ctrl_top/inst_sdram_ctrl/cycle_finished +add wave -noupdate -format Literal /tb_ctrl_sdr_wb32/uut/sdram_ctrl_frontend_wb16/inst_sdram_ctrl_top/inst_sdram_ctrl/seq_cnt +add wave -noupdate -format Logic /tb_ctrl_sdr_wb32/uut/sdram_ctrl_frontend_wb16/inst_sdram_ctrl_top/inst_sdram_ctrl/seq_rst_en +add wave -noupdate -format Logic /tb_ctrl_sdr_wb32/uut/sdram_ctrl_frontend_wb16/inst_sdram_ctrl_top/inst_sdram_ctrl/seq_cnt_en +add wave -noupdate -format Literal /tb_ctrl_sdr_wb32/uut/sdram_ctrl_frontend_wb16/inst_sdram_ctrl_top/inst_sdram_ctrl/refresh_cnt +add wave -noupdate -format Logic /tb_ctrl_sdr_wb32/uut/sdram_ctrl_frontend_wb16/inst_sdram_ctrl_top/inst_sdram_ctrl/refresh_request +add wave -noupdate -format Logic /tb_ctrl_sdr_wb32/uut/sdram_ctrl_frontend_wb16/inst_sdram_ctrl_top/inst_sdram_ctrl/refresh_cnt_rst +add wave -noupdate -format Logic /tb_ctrl_sdr_wb32/uut/sdram_ctrl_frontend_wb16/inst_sdram_ctrl_top/inst_sdram_ctrl/addr_reg_load_en +add wave -noupdate -format Literal /tb_ctrl_sdr_wb32/uut/sdram_ctrl_frontend_wb16/inst_sdram_ctrl_top/inst_sdram_ctrl/u_tag_reg +add wave -noupdate -format Literal /tb_ctrl_sdr_wb32/uut/sdram_ctrl_frontend_wb16/inst_sdram_ctrl_top/inst_sdram_ctrl/bank_addr_reg +add wave -noupdate -format Literal /tb_ctrl_sdr_wb32/uut/sdram_ctrl_frontend_wb16/inst_sdram_ctrl_top/inst_sdram_ctrl/row_addr_reg +add wave -noupdate -format Literal /tb_ctrl_sdr_wb32/uut/sdram_ctrl_frontend_wb16/inst_sdram_ctrl_top/inst_sdram_ctrl/col_addr_reg +add wave -noupdate -format Literal /tb_ctrl_sdr_wb32/uut/sdram_ctrl_frontend_wb16/inst_sdram_ctrl_top/inst_sdram_ctrl/bank_addr_last +add wave -noupdate -format Literal /tb_ctrl_sdr_wb32/uut/sdram_ctrl_frontend_wb16/inst_sdram_ctrl_top/inst_sdram_ctrl/row_addr_last +add wave -noupdate -format Literal /tb_ctrl_sdr_wb32/uut/sdram_ctrl_frontend_wb16/inst_sdram_ctrl_top/inst_sdram_ctrl/col_addr_last +add wave -noupdate -format Literal /tb_ctrl_sdr_wb32/uut/sdram_ctrl_frontend_wb16/inst_sdram_ctrl_top/inst_sdram_ctrl/u_bank_addr +add wave -noupdate -format Literal /tb_ctrl_sdr_wb32/uut/sdram_ctrl_frontend_wb16/inst_sdram_ctrl_top/inst_sdram_ctrl/u_row_addr +add wave -noupdate -format Literal /tb_ctrl_sdr_wb32/uut/sdram_ctrl_frontend_wb16/inst_sdram_ctrl_top/inst_sdram_ctrl/u_col_addr +add wave -noupdate -format Literal /tb_ctrl_sdr_wb32/uut/sdram_ctrl_frontend_wb16/inst_sdram_ctrl_top/inst_sdram_ctrl/bank_active_reg +add wave -noupdate -format Logic /tb_ctrl_sdr_wb32/uut/sdram_ctrl_frontend_wb16/inst_sdram_ctrl_top/inst_sdram_ctrl/bank_is_active +add wave -noupdate -format Logic /tb_ctrl_sdr_wb32/uut/sdram_ctrl_frontend_wb16/inst_sdram_ctrl_top/inst_sdram_ctrl/bank_activate +add wave -noupdate -format Logic /tb_ctrl_sdr_wb32/uut/sdram_ctrl_frontend_wb16/inst_sdram_ctrl_top/inst_sdram_ctrl/bank_clr TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 1} {73212560 ps} 0} +WaveRestoreCursors {{Cursor 1} {119525000 ps} 0} configure wave -namecolwidth 150 configure wave -valuecolwidth 100 configure wave -justifyvalue left @@ -95,4 +146,4 @@ configure wave -gridperiod 1 configure wave -griddelta 40 configure wave -timeline 0 update -WaveRestoreZoom {0 ps} {210 us} +WaveRestoreZoom {0 ps} {126 us} diff --git a/lib/SDRAM/ddr_sdr_v1_5/src/sdram_cmd.vhd b/lib/SDRAM/ddr_sdr_v1_5/src/sdram_cmd.vhd index e51125a..ff119c7 100644 --- a/lib/SDRAM/ddr_sdr_v1_5/src/sdram_cmd.vhd +++ b/lib/SDRAM/ddr_sdr_v1_5/src/sdram_cmd.vhd @@ -51,6 +51,9 @@ end sdram_cmd; architecture behaviour of sdram_cmd is + subtype cycle_cnt_t is natural range 0 to 15; + subtype burst_cnt_t is natural range 0 to 2**(LMR_BL_CURR)-1; + signal st_sdr, st_sdr_next : sdr_state_t; signal cc_preset : natural range 0 to 15; @@ -59,8 +62,7 @@ architecture behaviour of sdram_cmd is signal burst_load_en : std_logic; signal burst_finished : std_logic; - - subtype cycle_cnt_t is natural range 0 to 15; + signal burst_cnt : burst_cnt_t; type part_timing_array_t is array (sdr_cmd_t) of cycle_cnt_t; constant TIMING : part_timing_array_t := @@ -163,36 +165,38 @@ fsm_sdr_state: when WRITE => phy_ctrl.drive_en <= '1'; phy_ctrl.we <= '1'; - if burst_finished = '1' then - if cmd_we = '1' and cmd = SD_WRITE then - phy_ctrl.part.addr(col_addr_t'range) <= col_addr; - cmd_ack <= '1'; + phy_ctrl.part.cmd <= COMMAND(SD_NOP); + if cmd_we = '1' and cmd = SD_WRITE then + cmd_ack <= '1'; + phy_ctrl.utag_we <= '1'; + phy_ctrl.part.addr(col_addr_t'range) <= col_addr; + if burst_finished = '1' then burst_load_en <= '1'; phy_ctrl.part.cmd <= COMMAND(cmd); - phy_ctrl.utag_we <= '1'; - else - phy_ctrl.drive_en <= '0'; - cc_load_en <= '1'; - cc_preset <= TIMING(SD_WRITE)+1; - st_sdr_next <= ROW_ACT; end if; - end if; + else + phy_ctrl.drive_en <= '0'; + cc_load_en <= '1'; + cc_preset <= TIMING(SD_WRITE)+1; + st_sdr_next <= ROW_ACT; + end if; when READ => phy_ctrl.re <= '1'; - if burst_finished = '1' then - if cmd_we = '1' and cmd = SD_READ then - phy_ctrl.part.addr(col_addr_t'range) <= col_addr; - cmd_ack <= '1'; + phy_ctrl.part.cmd <= COMMAND(SD_NOP); + if cmd_we = '1' and cmd = SD_READ then + cmd_ack <= '1'; + phy_ctrl.utag_we <= '1'; + phy_ctrl.part.addr(col_addr_t'range) <= col_addr; + if burst_finished = '1' then burst_load_en <= '1'; phy_ctrl.part.cmd <= COMMAND(cmd); - phy_ctrl.utag_we <= '1'; - else - cc_load_en <= '1'; - cc_preset <= TIMING(SD_READ); - st_sdr_next <= ROW_ACT; end if; - end if; + else + cc_load_en <= '1'; + cc_preset <= TIMING(SD_READ); + st_sdr_next <= ROW_ACT; + end if; when WRITE_A => -- not implemented yet cmd_ack <= '1'; @@ -265,19 +269,18 @@ cycle_counter: ------------------------------------------------------------------------------------------ burst_counter: process (clk) - variable burst_cnt : natural range 0 to 2**(LMR_BL_CURR); begin if rising_edge(clk) then if burst_load_en = '1' then burst_finished <= '0'; - burst_cnt := 2**(LMR_BL_CURR); + burst_cnt <= burst_cnt_t'high; if 2**(LMR_BL_CURR) = DATA_RATE_FACTOR then burst_finished <= '1'; end if; - elsif burst_cnt < DATA_RATE_FACTOR then + elsif burst_cnt <= DATA_RATE_FACTOR then burst_finished <= '1'; else - burst_cnt := burst_cnt - DATA_RATE_FACTOR; + burst_cnt <= burst_cnt - DATA_RATE_FACTOR; end if; end if; end process; diff --git a/lib/SDRAM/ddr_sdr_v1_5/src/sdram_config_mt48lc16m16.vhd b/lib/SDRAM/ddr_sdr_v1_5/src/sdram_config_mt48lc16m16.vhd index fa51e2d..71e569f 100644 --- a/lib/SDRAM/ddr_sdr_v1_5/src/sdram_config_mt48lc16m16.vhd +++ b/lib/SDRAM/ddr_sdr_v1_5/src/sdram_config_mt48lc16m16.vhd @@ -47,7 +47,7 @@ package sdram_config is constant BIT_PRE_ALL : positive := 10; -- bit-position in column address for precharge all (see Data Sheet) constant ENABLE_PRE_ALL : std_logic := '1'; constant ENABLE_AUTO_PRE : std_logic := '0'; - constant LMR_BL_CURR : natural := LMR_BL1; + constant LMR_BL_CURR : natural := LMR_BL8; -- DDR-SDR TIMING constants ------------------------------------------------------------------ -- After REFRESH_CLOCKS a refresh cycle is necessary, 64ms / 8192 = max every 7.8125 us refesh