From d059cf8109b5c2b0a1a8fd53db1d19f25860e00a Mon Sep 17 00:00:00 2001 From: Jens Ahrensfeld Date: Sat, 10 Jan 2009 17:40:32 +0000 Subject: [PATCH] - new signal 'start' to trigger FIR process use din_vld for data load. This permits decimation FIR filtering git-svn-id: http://moon:8086/svn/vhdl/trunk@217 cc03376c-175c-47c8-b038-4cd826a8556b --- lib/filter/src/fir_semi_parallel.vhd | 29 +++++- lib/filter/src/tb_fir_semi_parallel.vhd | 115 +++++++++++++++--------- 2 files changed, 96 insertions(+), 48 deletions(-) diff --git a/lib/filter/src/fir_semi_parallel.vhd b/lib/filter/src/fir_semi_parallel.vhd index 2e57844..aabc7e8 100644 --- a/lib/filter/src/fir_semi_parallel.vhd +++ b/lib/filter/src/fir_semi_parallel.vhd @@ -58,6 +58,7 @@ Port din_vld : in std_logic; din : in sfixed; dout_vld : out std_logic; + start : in std_logic; rdy : out std_logic; dout : out sfixed ); @@ -103,10 +104,11 @@ architecture Behavioral of fir_semi_parallel is ------------------------------------------------------------------------------- begin + assert nstages > 0 report "nstages must be greater than 0!" severity failure; assert ntaps_per_stage = NextPowerOfTwo(ntaps_per_stage) report "ntaps_per_stage must be of form 2**R!" severity failure; assert ntaps_per_stage >= 4 report "ntaps_per_stage must be greater than 4" severity failure; - x(0) <= resize(din_r, x(0)); + x(0) <= resize(din, x(0)); y(0) <= to_sfixed(0.0, y(0)); accu_load <= accu_ld_pipe(accu_ld_pipe'left); @@ -168,7 +170,7 @@ counter: end if; else en <= '0'; - if din_vld = '1' then + if start = '1' then en <= '1'; cnt := 0; ce0 <= '1'; @@ -256,10 +258,29 @@ gen_stages: end generate; +inst_first_delay_line : entity work.delay_line(ram_based) + GENERIC MAP + ( + nbits => nbits_stages, + nbits_frac => nbits_stages_frac, + ntaps => ntaps_per_stage, + delay_fix => 0 + ) + PORT MAP + ( + rst => rst, + clk => clk, + ce => '1', + shift_en => din_vld, + delay => count_array(0), + din => x(0), + dout => x(1) + ); + gen_delays: - for i in 0 to nstages-1 generate + for i in 1 to nstages-1 generate begin - inst_delay_line : entity work.delay_line(ram_based) + inst_delay_lines : entity work.delay_line(ram_based) GENERIC MAP ( nbits => nbits_stages, diff --git a/lib/filter/src/tb_fir_semi_parallel.vhd b/lib/filter/src/tb_fir_semi_parallel.vhd index 810168f..bf6ee5d 100644 --- a/lib/filter/src/tb_fir_semi_parallel.vhd +++ b/lib/filter/src/tb_fir_semi_parallel.vhd @@ -31,8 +31,8 @@ use work.PCK_FIO.all; ENTITY tb_fir_semi_parallel IS Generic ( - ntaps_per_stage : integer := 32; - nstages : integer := 2; + ntaps_per_stage : integer := 16; + nstages : integer := 4; nbits_in : integer := 32; nbits_in_frac : integer := 30; nbits_stages : integer := 32; @@ -47,7 +47,7 @@ ARCHITECTURE behavior OF tb_fir_semi_parallel IS ------------------------------------------------------------------------------- --Constants constant PERIOD : time := 10 ns; - constant zero_in : sfixed := to_sfixed(0, nbits_in, nbits_in_frac); + constant nsamples : integer := 32; --Inputs SIGNAL clk : std_logic := '0'; @@ -57,6 +57,7 @@ ARCHITECTURE behavior OF tb_fir_semi_parallel IS signal h_addr : natural := 0; SIGNAL h_we : std_logic := '0'; SIGNAL h_in : sfixed(shi(nbits_stages, nbits_stages_frac) downto slo(nbits_stages, nbits_stages_frac)); + SIGNAL start : std_logic := '0'; --Outputs SIGNAL d_out : sfixed(shi(nbits_out, nbits_out_frac) downto slo(nbits_out, nbits_out_frac)); @@ -87,6 +88,43 @@ ARCHITECTURE behavior OF tb_fir_semi_parallel IS -- file I/O subtype sample_t is integer range -32768 to 32767; type file_t is file of sample_t; + + signal x_input : real_array_t(0 to nsamples-1) := + ( + 0.0, + 0.0, + 0.0, + 0.0, + 0.0, + 0.0, + 0.0, + 0.0, + 0.0, + 0.0, + 0.0, + 0.0, + 0.0, + 0.0, + 0.0, + 0.9999, + -0.0000, + 0.0, + 0.0, + 0.0, + 0.0, + 0.0, + 0.0, + 0.0, + 0.0, + 0.0, + 0.0, + 0.0, + 0.0, + 0.0, + 0.0, + 0.0 + + ); ------------------------------------------------------------------------------- BEGIN @@ -102,7 +140,7 @@ BEGIN ( ntaps_per_stage => ntaps_per_stage, nstages => nstages, - mul_latency => 2, + mul_latency => 5, nbits_in => nbits_in, nbits_in_frac => nbits_in_frac, nbits_stages => nbits_stages, @@ -121,6 +159,7 @@ BEGIN din => d_in, dout_vld => dout_vld, rdy => rdy, + start => start, dout => d_out ); @@ -160,51 +199,39 @@ BEGIN wait until rising_edge(clk); h_we <= '0'; - d_in <= to_sfixed(0.0, d_in); - wait for 64*ntaps*PERIOD; - wait until rising_edge(clk); - - for i in 0 to 19 loop + -- Write zeros + for i in 0 to ntaps_per_stage*nstages-1 loop wait until rising_edge(clk) and rdy = '1'; - din_vld <= '1'; - d_in <= to_sfixed(real(i)*0.01, d_in); - wait until rising_edge(clk); - din_vld <= '0'; - end loop; - wait until rising_edge(clk) and rdy = '1'; - ------------------------------------------ - din_vld <= '1'; - d_in <= to_sfixed(0.0, d_in); - wait for 64*ntaps*PERIOD; - wait until rising_edge(clk); - din_vld <= '0'; - - wait for 64*ntaps*PERIOD; - - wait until rising_edge(clk) and rdy = '1'; - din_vld <= '1'; - d_in <= to_sfixed(1.0, d_in); - wait until rising_edge(clk); - din_vld <= '0'; - - wait for 10*PERIOD; - wait until rising_edge(clk) and rdy = '1'; - din_vld <= '1'; - d_in <= to_sfixed(0.0, d_in); - wait until rising_edge(clk); - din_vld <= '0'; - - for i in 0 to 9999 loop - wait for 2*PERIOD; - wait until rising_edge(clk) and rdy = '1'; - din_vld <= '1'; d_in <= to_sfixed(0.0, d_in); + din_vld <= '1'; + start <= '1'; wait until rising_edge(clk); din_vld <= '0'; - + start <= '0'; + end loop; + + ------------------------------------------ + -- Write data + for i in 0 to nsamples-1 loop + wait until rising_edge(clk) and rdy = '1'; + d_in <= to_sfixed(x_input(i), d_in); + din_vld <= '1'; + start <= '1'; + wait until rising_edge(clk); + din_vld <= '0'; + start <= '0'; + end loop; + + -- Write zeros + for i in 0 to 99 loop + wait until rising_edge(clk) and rdy = '1'; + d_in <= to_sfixed(0.0, d_in); + din_vld <= '1'; + start <= '1'; + wait until rising_edge(clk); + din_vld <= '0'; + start <= '0'; end loop; - - wait for 40*PERIOD; assert false report "Test finished" severity error; wait;