From ce636ef1ec9d96eddbf57b52a07f82fc7328a961 Mon Sep 17 00:00:00 2001 From: Jens Ahrensfeld Date: Sun, 24 May 2015 08:15:35 +0000 Subject: [PATCH] - introduced phy_in_t and phy_out_t git-svn-id: http://moon:8086/svn/vhdl/trunk@1189 cc03376c-175c-47c8-b038-4cd826a8556b --- .../ddr_sdr_v1_5/src/ddr_phy_virtex4.vhd | 37 ++++++++---------- .../src/sdram_ctrl_frontend64_wb.vhd | 39 +++++++------------ .../src/sdram_ctrl_frontend_wb.vhd | 32 +++++++-------- lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_top.vhd | 24 ++++-------- lib/SDRAM/ddr_sdr_v1_5/src/sdram_types.vhd | 15 +++++++ 5 files changed, 65 insertions(+), 82 deletions(-) diff --git a/lib/SDRAM/ddr_sdr_v1_5/src/ddr_phy_virtex4.vhd b/lib/SDRAM/ddr_sdr_v1_5/src/ddr_phy_virtex4.vhd index bebabef..cfad6cd 100644 --- a/lib/SDRAM/ddr_sdr_v1_5/src/ddr_phy_virtex4.vhd +++ b/lib/SDRAM/ddr_sdr_v1_5/src/ddr_phy_virtex4.vhd @@ -43,13 +43,8 @@ entity sdram_phy is clk_fb : in STD_LOGIC; clk0_out : out STD_LOGIC; rst0_out : out STD_LOGIC; - u_tag_rd : out user_tag_t; - u_tag_wr : out user_tag_t; - u_wr_data : in unsigned(SDR_DATA_WIDTH-1 downto 0); - u_dm : in unsigned(SDR_DM_WIDTH-1 downto 0); - u_rd_data : out unsigned(SDR_DATA_WIDTH-1 downto 0); - u_rd_data_we : out STD_LOGIC; - u_wr_data_re : out STD_LOGIC; + phy_in : in phy_in_t; + phy_out : out phy_out_t; phy_ctrl : in phy_ctrl_t; part_clk_p : out STD_LOGIC; part_clk_n : out STD_LOGIC; @@ -233,8 +228,8 @@ gen_ddr_data_out: Q => ddr_data_w(n), -- 1-bit DDR output C => clk_wr, -- 1-bit clock input CE => '1', -- 1-bit clock enable input - D1 => u_wr_data(n + DDR_DATA_WIDTH), -- 1-bit data input (positive edge) - D2 => u_wr_data(n), -- 1-bit data input (negative edge) + D1 => phy_in.wr_data(n + DDR_DATA_WIDTH), -- 1-bit data input (positive edge) + D2 => phy_in.wr_data(n), -- 1-bit data input (negative edge) R => '0', -- 1-bit reset input S => '0' -- 1-bit set input ); @@ -272,8 +267,8 @@ gen_ddr_dm_out: Q => part_dm(n), -- 1-bit DDR output C => clk_wr, -- 1-bit clock input CE => '1', -- 1-bit clock enable input - D1 => u_dm(n + DDR_DM_WIDTH), -- 1-bit data input (positive edge) - D2 => u_dm(n), -- 1-bit data input (negative edge) + D1 => phy_in.wr_dm(n + DDR_DM_WIDTH), -- 1-bit data input (positive edge) + D2 => phy_in.wr_dm(n), -- 1-bit data input (negative edge) R => '0', -- 1-bit reset input S => '0' -- 1-bit set input ); @@ -395,21 +390,21 @@ misc_flags_and_data_out: begin if rising_edge(clk0) then if rst0 = '1' then - p := (others => '0'); - read_en <= '0'; - u_rd_data_we <= '0'; - u_wr_data_re <= '0'; + p := (others => '0'); + read_en <= '0'; + phy_out.rd_data_we <= '0'; + phy_out.wr_data_re <= '0'; else - u_rd_data <= data_reg_r; + phy_out.rd_data <= data_reg_r; if p(3) = '1' then - u_tag_rd <= u_tag_pipe(4); + phy_out.tag_rd <= u_tag_pipe(4); end if; if phy_ctrl.we = '1' then - u_tag_wr <= u_tag_pipe(0); + phy_out.tag_wr <= u_tag_pipe(0); end if; - u_wr_data_re <= phy_ctrl.we; - u_rd_data_we <= p(3); - read_en <= p(1); + phy_out.wr_data_re <= phy_ctrl.we; + phy_out.rd_data_we <= p(3); + read_en <= p(1); if phy_ctrl.re = '1' then p := p(p'left-1 downto 0) & '1'; else diff --git a/lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_frontend64_wb.vhd b/lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_frontend64_wb.vhd index 47c4352..cfd6149 100644 --- a/lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_frontend64_wb.vhd +++ b/lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_frontend64_wb.vhd @@ -77,18 +77,14 @@ architecture struct of sdram_ctrl_frontend64_wb is signal SDRAM_CLK0 : std_logic; signal SDRAM_RST0 : std_logic; + signal phy_in : phy_in_t; + signal phy_out : phy_out_t; + signal u_addr : user_addr_t; signal u_tag_in : user_tag_t; - signal u_tag_rd : user_tag_t; - signal u_tag_wr : user_tag_t; signal u_cmd : user_cmd_t; signal u_cmd_we : std_logic; signal u_busy : std_logic; - signal u_data_w : unsigned(SDR_DATA_WIDTH-1 downto 0); - signal u_dm_wr_in : unsigned(SDR_DM_WIDTH-1 downto 0); - signal u_data_r : unsigned(SDR_DATA_WIDTH-1 downto 0); - signal u_rd_data_we : std_logic; - signal u_wr_data_re : std_logic; signal rdy : std_logic; constant CAT_FIFO_WIDTH : integer := user_cmd_t'length + user_tag_t'length + DDR_ROW_ADDR_WIDTH + DDR_BANK_WIDTH + DDR_COL_ADDR_WIDTH; @@ -98,8 +94,6 @@ architecture struct of sdram_ctrl_frontend64_wb is signal cat_fifo_we : std_logic; signal cat_fifo_full : std_logic; signal cat_fifo_empty : std_logic; --- signal cat_fifo_almost_full : std_logic; --- signal cat_fifo_almost_empty : std_logic; signal write_fifo_din : unsigned(SDR_DATA_WIDTH+SDR_DM_WIDTH-1 downto 0); signal write_fifo_dout : unsigned(SDR_DATA_WIDTH+SDR_DM_WIDTH-1 downto 0); @@ -107,8 +101,6 @@ architecture struct of sdram_ctrl_frontend64_wb is signal write_fifo_we : std_logic; signal write_fifo_full : std_logic; signal write_fifo_empty : std_logic; --- signal write_fifo_almost_full : std_logic; --- signal write_fifo_almost_empty : std_logic; signal read_fifo_din : unsigned(SDR_DATA_WIDTH-1 downto 0); signal read_fifo_dout : unsigned(SDR_DATA_WIDTH-1 downto 0); @@ -116,8 +108,6 @@ architecture struct of sdram_ctrl_frontend64_wb is signal read_fifo_we : std_logic; signal read_fifo_full : std_logic; signal read_fifo_empty : std_logic; --- signal read_fifo_almost_full : std_logic; --- signal read_fifo_almost_empty : std_logic; alias cmd_fifo_in is cat_fifo_din(CAT_FIFO_WIDTH-1 downto CAT_FIFO_WIDTH-user_cmd_t'length); alias tag_fifo_in is cat_fifo_din(CAT_FIFO_WIDTH-user_cmd_t'length-1 downto CAT_FIFO_WIDTH-user_cmd_t'length-user_tag_t'length); @@ -222,19 +212,16 @@ begin sdram_rst_out => SDRAM_RST0, -- User interface - u_rd_data_we => u_rd_data_we, - u_wr_data_re => u_wr_data_re, - u_tag_in => u_tag_in, - u_tag_rd => u_tag_rd, - u_tag_wr => u_tag_wr, + u_tag => u_tag_in, u_busy => u_busy, u_addr => u_addr, u_cmd => u_cmd, u_cmd_we => u_cmd_we, - u_wr_data => u_data_w, - u_rd_data => u_data_r, - u_dm => u_dm_wr_in, + -- Phy user interface + phy_in => phy_in, + phy_out => phy_out, + -- SDRAM signals sd_clk_p => sd_clk_p, sd_clk_n => sd_clk_n, @@ -267,14 +254,14 @@ begin u_cmd_we <= (not cat_fifo_empty) and (not u_busy); u_cmd <= cmd_fifo_out; u_addr <= addr_fifo_out; - u_dm_wr_in <= (write_fifo_dm_out(SDR_DATA_WIDTH+SDR_DM_WIDTH-5 downto SDR_DATA_WIDTH) & write_fifo_dm_out(SDR_DATA_WIDTH+SDR_DM_WIDTH-1 downto SDR_DATA_WIDTH+4)) when u_tag_wr(0) = '1' else write_fifo_dm_out(SDR_DATA_WIDTH+SDR_DM_WIDTH-1 downto SDR_DATA_WIDTH); + phy_in.wr_dm <= (write_fifo_dm_out(SDR_DATA_WIDTH+SDR_DM_WIDTH-5 downto SDR_DATA_WIDTH) & write_fifo_dm_out(SDR_DATA_WIDTH+SDR_DM_WIDTH-1 downto SDR_DATA_WIDTH+4)) when phy_out.tag_wr(0) = '1' else write_fifo_dm_out(SDR_DATA_WIDTH+SDR_DM_WIDTH-1 downto SDR_DATA_WIDTH); u_tag_in <= tag_fifo_out; - u_data_w <= (write_fifo_data_out(31 downto 0) & write_fifo_data_out(63 downto 32)) when u_tag_wr(0) = '1' else write_fifo_data_out(63 downto 0); + phy_in.wr_data <= (write_fifo_data_out(31 downto 0) & write_fifo_data_out(63 downto 32)) when phy_out.tag_wr(0) = '1' else write_fifo_data_out(63 downto 0); - write_fifo_re <= u_wr_data_re and (not write_fifo_empty); + write_fifo_re <= phy_out.wr_data_re and (not write_fifo_empty); cat_fifo_re <= u_cmd_we; read_fifo_re <= (not read_fifo_empty) and MRDY_I; - read_fifo_we <= u_rd_data_we; - read_fifo_data_in <= (u_data_r(31 downto 0) & u_data_r(63 downto 32)) when u_tag_rd(0) = '1' else u_data_r(63 downto 0); + read_fifo_we <= phy_out.rd_data_we; + read_fifo_data_in <= (phy_out.rd_data(31 downto 0) & phy_out.rd_data(63 downto 32)) when phy_out.tag_rd(0) = '1' else phy_out.rd_data(63 downto 0); end architecture struct; diff --git a/lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_frontend_wb.vhd b/lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_frontend_wb.vhd index d4d4138..4525a29 100644 --- a/lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_frontend_wb.vhd +++ b/lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_frontend_wb.vhd @@ -77,6 +77,9 @@ architecture struct of sdram_ctrl_frontend_wb is signal SDRAM_CLK0 : std_logic; signal SDRAM_RST0 : std_logic; + signal phy_in : phy_in_t; + signal phy_out : phy_out_t; + signal u_addr : user_addr_t; signal u_tag_in : user_tag_t; signal u_tag_rd : user_tag_t; @@ -98,8 +101,6 @@ architecture struct of sdram_ctrl_frontend_wb is signal cat_fifo_we : std_logic; signal cat_fifo_full : std_logic; signal cat_fifo_empty : std_logic; --- signal cat_fifo_almost_full : std_logic; --- signal cat_fifo_almost_empty : std_logic; signal write_fifo_din : unsigned(35 downto 0); signal write_fifo_dout : unsigned(35 downto 0); @@ -107,8 +108,6 @@ architecture struct of sdram_ctrl_frontend_wb is signal write_fifo_we : std_logic; signal write_fifo_full : std_logic; signal write_fifo_empty : std_logic; --- signal write_fifo_almost_full : std_logic; --- signal write_fifo_almost_empty : std_logic; signal read_fifo_din : unsigned(31 downto 0); signal read_fifo_dout : unsigned(31 downto 0); @@ -116,8 +115,6 @@ architecture struct of sdram_ctrl_frontend_wb is signal read_fifo_we : std_logic; signal read_fifo_full : std_logic; signal read_fifo_empty : std_logic; --- signal read_fifo_almost_full : std_logic; --- signal read_fifo_almost_empty : std_logic; alias cmd_fifo_in is cat_fifo_din(CAT_FIFO_WIDTH-1 downto CAT_FIFO_WIDTH-user_cmd_t'length); alias tag_fifo_in is cat_fifo_din(CAT_FIFO_WIDTH-user_cmd_t'length-1 downto CAT_FIFO_WIDTH-user_cmd_t'length-user_tag_t'length); @@ -222,18 +219,15 @@ begin sdram_rst_out => SDRAM_RST0, -- User interface - u_rd_data_we => u_rd_data_we, - u_wr_data_re => u_wr_data_re, - u_tag_in => u_tag_in, - u_tag_rd => u_tag_rd, - u_tag_wr => u_tag_wr, + u_tag => u_tag_in, u_busy => u_busy, u_addr => u_addr, u_cmd => u_cmd, u_cmd_we => u_cmd_we, - u_wr_data => u_data_w, - u_rd_data => u_data_r, - u_dm => u_dm_wr_in, + + -- Phy user interface + phy_in => phy_in, + phy_out => phy_out, -- SDRAM signals sd_clk_p => sd_clk_p, @@ -267,14 +261,14 @@ begin u_cmd_we <= (not cat_fifo_empty) and (not u_busy); u_cmd <= cmd_fifo_out; u_addr <= addr_fifo_out; - u_dm_wr_in <= ("1111" & write_fifo_dm_out) when u_tag_wr(0) = '0' else (write_fifo_dm_out & "1111"); + phy_in.wr_dm <= ("1111" & write_fifo_dm_out) when phy_out.tag_wr(0) = '0' else (write_fifo_dm_out & "1111"); u_tag_in <= tag_fifo_out; - u_data_w <= write_fifo_data_out & write_fifo_data_out; + phy_in.wr_data <= write_fifo_data_out & write_fifo_data_out; - write_fifo_re <= u_wr_data_re and (not write_fifo_empty); + write_fifo_re <= phy_out.wr_data_re and (not write_fifo_empty); cat_fifo_re <= u_cmd_we; read_fifo_re <= (not read_fifo_empty) and MRDY_I; - read_fifo_we <= u_rd_data_we; - read_fifo_data_in <= u_data_r(31 downto 0) when u_tag_rd(0) = '0' else u_data_r(63 downto 32); + read_fifo_we <= phy_out.rd_data_we; + read_fifo_data_in <= phy_out.rd_data(31 downto 0) when phy_out.tag_rd(0) = '0' else phy_out.rd_data(63 downto 32); end architecture struct; diff --git a/lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_top.vhd b/lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_top.vhd index 541f98f..940f95b 100644 --- a/lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_top.vhd +++ b/lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_top.vhd @@ -47,19 +47,16 @@ entity sdram_ctrl_top is sdram_rst_out : out STD_LOGIC; -- User interface - u_rd_data_we : out STD_LOGIC; - u_wr_data_re : out STD_LOGIC; u_busy : out STD_LOGIC; u_cmd : in user_cmd_t; u_cmd_we : in STD_LOGIC; u_addr : in user_addr_t; - u_tag_in : in user_tag_t; - u_tag_rd : out user_tag_t; - u_tag_wr : out user_tag_t; - u_wr_data : in unsigned(SDR_DATA_WIDTH-1 downto 0); - u_dm : in unsigned(SDR_DM_WIDTH-1 downto 0); - u_rd_data : out unsigned(SDR_DATA_WIDTH-1 downto 0); + u_tag : in user_tag_t; + -- Phy user stuff + phy_in : in phy_in_t; + phy_out : out phy_out_t; + -- SDRAM signals sd_clk_p : out STD_LOGIC; sd_clk_n : out STD_LOGIC; @@ -136,7 +133,7 @@ begin rst => sys_rst_in, clk => sys_clk_in, u_busy => u_busy, - u_tag_in => u_tag_in, + u_tag_in => u_tag, u_tag_out => tag_fifo_in, u_cmd => u_cmd, u_cmd_we => u_cmd_we, @@ -204,13 +201,8 @@ begin clk_fb => sdram_clk_fb, clk0_out => sdram_clk0, rst0_out => sdram_rst0, - u_tag_rd => u_tag_rd, - u_tag_wr => u_tag_wr, - u_wr_data_re => u_wr_data_re, - u_wr_data => u_wr_data, - u_dm => u_dm, - u_rd_data => u_rd_data, - u_rd_data_we => u_rd_data_we, + phy_in => phy_in, + phy_out => phy_out, phy_ctrl => phy_ctrl, part_clk_p => sd_clk_p, part_clk_n => sd_clk_n, diff --git a/lib/SDRAM/ddr_sdr_v1_5/src/sdram_types.vhd b/lib/SDRAM/ddr_sdr_v1_5/src/sdram_types.vhd index e52e16e..98555e2 100644 --- a/lib/SDRAM/ddr_sdr_v1_5/src/sdram_types.vhd +++ b/lib/SDRAM/ddr_sdr_v1_5/src/sdram_types.vhd @@ -94,6 +94,21 @@ package sdram_types is u_tag : user_tag_t; end record phy_ctrl_t; + type phy_in_t is + record + wr_dm : unsigned(SDR_DM_WIDTH-1 downto 0); + wr_data : unsigned(SDR_DATA_WIDTH-1 downto 0); + end record phy_in_t; + + type phy_out_t is + record + rd_data : unsigned(SDR_DATA_WIDTH-1 downto 0); + rd_data_we : STD_LOGIC; + wr_data_re : STD_LOGIC; + tag_rd : user_tag_t; + tag_wr : user_tag_t; + end record phy_out_t; + type part_cmd_array_t is array (sdr_cmd_t) of sdr_cmd_lines_t; constant COMMAND : part_cmd_array_t := -- command cs_n ras_qn cas_qn we_qn