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- added command fifo for xfer unit

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- completed first version of receiver
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git-svn-id: http://moon:8086/svn/vhdl/trunk@811 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
jens
2010-03-23 11:34:28 +00:00
parent c3c2cdfe2b
commit cd285df8e8
5 changed files with 558 additions and 173 deletions
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lib/emac/src/emac_rx.vhd
+320 -52
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@@ -36,43 +36,55 @@ ARCHITECTURE behavior OF emac_rx IS
subtype word_ptr_t is unsigned(RAM_ADDR_WIDTH-1 downto 0);
-- Signals for EMAC connections
signal fifo_din : unsigned(35 downto 0);
signal fifo_dout : unsigned(35 downto 0);
signal fifo_we : std_logic;
signal fifo_re : std_logic;
signal fifo_empty : std_logic;
signal fifo_full : std_logic;
signal mii_fifo_din : unsigned(35 downto 0);
signal mii_fifo_dout : unsigned(35 downto 0);
signal mii_fifo_we : std_logic;
signal mii_fifo_re : std_logic;
signal mii_fifo_empty : std_logic;
signal mii_fifo_full : std_logic;
signal cmd_fifo_din : unsigned(35 downto 0);
signal cmd_fifo_dout : unsigned(35 downto 0);
signal cmd_fifo_we : std_logic;
signal cmd_fifo_re : std_logic;
signal cmd_fifo_empty : std_logic;
signal cmd_fifo_full : std_logic;
signal flush_en : std_logic;
signal flush_rdy : std_logic;
signal flush_ptr_set : std_logic;
signal flush_ptr : word_ptr_t;
signal fill_size : word_ptr_t;
signal fill_cnt : word_ptr_t;
signal fill_ptr : word_ptr_t;
signal fill_rdy : std_logic;
signal fill_cnt_set : std_logic;
signal fill_cnt_adv : std_logic;
signal fill_ptr_set : std_logic;
signal fill_ptr_adv : std_logic;
signal fill_remain : unsigned(1 downto 0);
signal nwords_free : word_ptr_t;
signal free_en : std_logic;
signal commit_en : std_logic;
signal uncommit_en : std_logic;
signal xfer_ram_full : std_logic;
signal xfer_base : word_ptr_t;
signal xfer_size : word_ptr_t;
signal xfer_ptr : word_ptr_t;
signal xfer_ptr_next : word_ptr_t;
signal xfer_cnt : word_ptr_t;
signal xfer_ptr_set : std_logic;
signal xfer_ptr_adv : std_logic;
signal xfer_cnt_set : std_logic;
signal xfer_cnt_adv : std_logic;
signal xfer_rdy : std_logic;
signal xfer_tag : unsigned(3 downto 0);
signal xfer_remain : unsigned(1 downto 0);
signal xfer_odd : std_logic;
signal xfer_remain_en : std_logic;
signal ram_en_a : std_logic;
signal ram_we_a : std_logic;
signal ram_addr_a : word_ptr_t;
signal ram_din_a : unsigned(35 downto 0);
signal ram_dout_a : unsigned(35 downto 0);
signal ram_din_a : unsigned(31 downto 0);
signal ram_dout_a : unsigned(31 downto 0);
signal ram_en_b : std_logic;
signal ram_we_b : std_logic;
signal ram_addr_b : word_ptr_t;
signal ram_din_b : unsigned(35 downto 0);
signal ram_dout_b : unsigned(35 downto 0);
signal ram_din_b : unsigned(31 downto 0);
signal ram_dout_b : unsigned(31 downto 0);
signal sipo_dout : unsigned(31 downto 0);
signal sipo_dout_be : unsigned(3 downto 0);
@@ -81,26 +93,125 @@ ARCHITECTURE behavior OF emac_rx IS
signal byte_count : word_ptr_t;
signal byte_count_reg : word_ptr_t;
signal byte_count_reg_s : word_ptr_t;
signal word_count : word_ptr_t;
signal word_count_reg : word_ptr_t;
signal word_count_set : std_logic;
signal word_count_clr : std_logic;
signal word_count_ack : std_logic;
signal word_count_vld : std_logic;
signal rx_dv_r : std_logic;
type host_state_t is (host_init, host_flush, host_idle, host_setup, host_arm, host_fill, host_uncommit);
signal host_s, host_sn : host_state_t;
type xfer_state_t is (xfer_init, xfer_idle, xfer_setup, xfer_wait, xfer_active, xfer_free);
signal xfer_s, xfer_sn : xfer_state_t;
alias ram_data_in_a is ram_din_a(31 downto 0);
alias ram_tag_in_a is ram_din_a(35 downto 32);
alias ram_data_out_a is ram_dout_a(31 downto 0);
alias ram_tag_out_a is ram_dout_a(35 downto 32);
alias ram_data_in_b is ram_din_b(31 downto 0);
alias ram_tag_in_b is ram_din_b(35 downto 32);
alias ram_data_out_b is ram_dout_b(31 downto 0);
alias ram_tag_out_b is ram_dout_b(35 downto 32);
begin
dout <= sipo_dout;
fifo_din <= sipo_dout_be & sipo_dout;
ctrl_out.rx_size <= cmd_fifo_dout(31 downto 16);
ctrl_out.rx_vld <= not cmd_fifo_empty;
ctrl_out.rx_er <= mii_rx_er;
dout <= ram_dout_a;
mii_fifo_din <= sipo_dout_be & sipo_dout;
mii_fifo_we <= sipo_dout_vld;
ram_en_a <= ctrl_in.data_read;
ram_din_a <= (others => '-');
ram_addr_a <= fill_ptr;
ram_we_a <= '0';
ram_en_b <= '1';
ram_din_b <= mii_fifo_dout(31 downto 0);
ram_addr_b <= xfer_ptr;
ram_we_b <= xfer_cnt_adv;
cmd_fifo_we <= commit_en;
cmd_fifo_re <= uncommit_en;
cmd_fifo_din <= "0000" & resize(byte_count_reg_s, 16) & resize(xfer_base, 16);
------------------------------------------------------------------
host_state_next:
process(clk)
begin
if rising_edge(clk) then
if rst = '1' then
host_s <= host_init;
else
host_s <= host_sn;
end if;
end if;
end process;
host_state:
process(host_s, cmd_fifo_empty, ctrl_in.data_read, ctrl_in.uncommit)
begin
flush_en <= '0';
fill_ptr_set <= '0';
fill_ptr_adv <= '0';
uncommit_en <= '0';
host_sn <= host_s;
case host_s is
when host_init =>
flush_en <= '1';
host_sn <= host_flush;
when host_flush =>
flush_en <= '1';
host_sn <= host_idle;
when host_idle =>
if cmd_fifo_empty = '0' then
host_sn <= host_setup;
end if;
when host_setup =>
fill_ptr_set <= '1';
host_sn <= host_arm;
when host_arm =>
host_sn <= host_fill;
when host_fill =>
fill_ptr_adv <= ctrl_in.data_read;
if ctrl_in.uncommit = '1' then
host_sn <= host_uncommit;
end if;
when host_uncommit =>
uncommit_en <= '1';
host_sn <= host_idle;
when others =>
host_sn <= host_idle;
end case;
end process;
------------------------------------------------------------------
-- Fill stuff
------------------------------------------------------------------
fill_pointer:
process(clk)
begin
if rising_edge(clk) then
ctrl_out.data_vld <= ctrl_in.data_read;
if fill_ptr_set = '1' then
fill_ptr <= resize(cmd_fifo_dout(15 downto 0), word_ptr_t'length);
elsif fill_ptr_adv = '1' then
fill_ptr <= fill_ptr + 1;
end if;
end if;
end process;
------------------------------------------------------------------
-- Transfer stuff
------------------------------------------------------------------
@@ -117,34 +228,53 @@ xfer_state_next:
end process;
xfer_state:
process(xfer_s, mii_rx_dv)
process(xfer_s, mii_fifo_empty, xfer_rdy, xfer_ram_full)
begin
commit_en <= '0';
xfer_ptr_set <= '0';
xfer_ptr_adv <= '0';
xfer_cnt_set <= '0';
xfer_cnt_adv <= '0';
word_count_ack <= '0';
mii_fifo_re <= '0';
xfer_sn <= xfer_s;
case xfer_s is
when xfer_init =>
xfer_sn <= xfer_idle;
xfer_sn <= xfer_idle;
when xfer_idle =>
xfer_sn <= xfer_setup;
if mii_fifo_empty = '0' then
xfer_sn <= xfer_setup;
end if;
when xfer_setup =>
xfer_cnt_set <= '1';
xfer_ptr_set <= '1';
xfer_sn <= xfer_wait;
when xfer_wait =>
if mii_rx_dv = '1' then
xfer_sn <= xfer_active;
end if;
xfer_sn <= xfer_active;
when xfer_active =>
if mii_rx_dv = '0' then
mii_fifo_re <= '1';
xfer_cnt_adv <= not mii_fifo_empty;
xfer_ptr_adv <= not mii_fifo_empty;
if xfer_ram_full = '1' then
xfer_sn <= xfer_free;
elsif xfer_rdy = '1' then
if mii_fifo_empty = '1' then
xfer_sn <= xfer_free;
end if;
end if;
when xfer_free =>
xfer_sn <= xfer_init;
word_count_ack <= '1';
commit_en <= not xfer_ram_full;
xfer_sn <= xfer_idle;
when others =>
xfer_sn <= xfer_idle;
@@ -152,6 +282,66 @@ xfer_state:
end process;
------------------------------------------------------------------
xfer_ram_full_detect:
process(clk)
begin
if rising_edge(clk) then
if xfer_ptr_set = '1' or flush_en = '1' then
xfer_ram_full <= '0';
elsif xfer_ptr_adv = '1' then
if xfer_ptr_next = resize(cmd_fifo_dout(15 downto 0), word_ptr_t'length) then
xfer_ram_full <= '1';
end if;
end if;
end if;
end process;
xfer_counter:
process(clk)
begin
if rising_edge(clk) then
xfer_rdy <= '0';
if xfer_size = word_count_reg then
xfer_rdy <= word_count_vld;
end if;
if xfer_cnt_set = '1' then
xfer_size <= (others => '0');
elsif xfer_cnt_adv = '1' then
xfer_size <= xfer_size + 1;
end if;
end if;
end process;
xfer_pointer:
process(clk)
begin
if rising_edge(clk) then
if xfer_ptr_set = '1' then
xfer_ptr <= xfer_base;
xfer_ptr_next <= xfer_base + 1;
elsif xfer_ptr_adv = '1' then
xfer_ptr <= xfer_ptr_next;
xfer_ptr_next <= xfer_ptr_next + 1;
end if;
end if;
end process;
xfer_base_logic:
process(clk)
begin
if rising_edge(clk) then
if flush_en = '1' then
xfer_base <= (others => '0');
elsif commit_en = '1' then
xfer_base <= xfer_ptr;
end if;
end if;
end process;
------------------------------------------------------------------
byte_counter:
process(mii_rx_clk)
@@ -178,13 +368,91 @@ byte_count_register:
end if;
end process;
word_counter:
process(mii_rx_clk)
begin
if rising_edge(mii_rx_clk) then
if rst = '1' or word_count_clr = '1' then
word_count <= (others => '0');
elsif sipo_dout_vld = '1' then
word_count <= word_count + 1;
end if;
end if;
end process;
-- MII doamin
word_count_set_logic:
process(mii_rx_clk)
begin
if rising_edge(mii_rx_clk) then
if rst = '1' or word_count_clr = '1' then
word_count_set <= '0';
elsif sipo_dout_vld = '1' and mii_rx_dv = '0' then
word_count_set <= '1';
end if;
end if;
end process;
-- Host doamin
word_count_clr_logic:
process(clk)
begin
if rising_edge(clk) then
if rst = '1' then
word_count_clr <= '0';
elsif word_count_set = '1' then
if word_count_ack = '1' then
word_count_clr <= '1';
end if;
else
word_count_clr <= '0';
end if;
end if;
end process;
word_count_register:
process(clk)
begin
if rising_edge(clk) then
if rst = '1' or word_count_ack = '1' then
word_count_vld <= '0';
elsif word_count_set = '1' then
word_count_reg <= word_count;
byte_count_reg_s <= byte_count_reg;
word_count_vld <= '1';
end if;
end if;
end process;
sipo_rst <= not mii_rx_dv;
------------------------------------------------------------------
-- Instantiate synchronous FIFO
inst_cmd_fifo: entity work.fifo_sync
GENERIC MAP
(
addr_width => NextExpBaseTwo(RAM_SIZE) - 4, -- RAMSIZE(words)/MIN_PACKET_LEN(words)
data_width => cmd_fifo_din'length,
do_last_read_update => true
)
PORT MAP
(
rst => flush_en,
clk => clk,
we => cmd_fifo_we,
re => cmd_fifo_re,
fifo_full => cmd_fifo_full,
fifo_empty => cmd_fifo_empty,
fifo_afull => open,
fifo_aempty => open,
data_w => cmd_fifo_din,
data_r => cmd_fifo_dout
);
inst_ram : entity work.dpram_2w2r
GENERIC MAP
(
addr_width => RAM_ADDR_WIDTH,
data_width => 36
data_width => 32
)
PORT MAP
(
@@ -203,7 +471,7 @@ inst_ram : entity work.dpram_2w2r
);
-- Instantiate synchronous FIFO
inst_fifo: entity work.fifo_async
inst_mii_fifo: entity work.fifo_async
GENERIC MAP
(
addr_width => 5,
@@ -213,16 +481,16 @@ inst_fifo: entity work.fifo_async
PORT MAP
(
rst => rst,
clk_w => clk,
clk_r => mii_rx_clk,
we => fifo_we,
re => fifo_re,
fifo_full => fifo_full,
fifo_empty => fifo_empty,
clk_w => mii_rx_clk,
clk_r => clk,
we => mii_fifo_we,
re => mii_fifo_re,
fifo_full => mii_fifo_full,
fifo_empty => mii_fifo_empty,
fifo_afull => open,
fifo_aempty => open,
data_w => fifo_din,
data_r => fifo_dout
data_w => mii_fifo_din,
data_r => mii_fifo_dout
);
inst_sipo : entity work.sipo