From cbd6a1fa29ea5ff17e8a7e90f608edb80740aa78 Mon Sep 17 00:00:00 2001
From: Jens Ahrensfeld <jens@jayfield.org>
Date: Sun, 4 Apr 2021 08:57:50 +0000
Subject: [PATCH] - added

git-svn-id: http://moon:8086/svn/vhdl/trunk@1630 cc03376c-175c-47c8-b038-4cd826a8556b
---
 lib/CPUs/JCpu/src/cpu_embedded_with_uart.vhd  |  229 ++++
 lib/CPUs/JCpu/src/hallo_welt_uart_irom.vhdl   |  184 +++
 .../JCpu/src/hallo_welt_uart_irom_ld.vhdl     | 1181 +++++++++++++++++
 lib/CPUs/JCpu/src/hallo_welt_uart_xrom.vhdl   |  317 +++++
 .../JCpu/src/hallo_welt_uart_xrom_ld.vhdl     |  413 ++++++
 .../JCpu/src/tb_cpu_embedded_with_uart.vhd    |  132 ++
 6 files changed, 2456 insertions(+)
 create mode 100644 lib/CPUs/JCpu/src/cpu_embedded_with_uart.vhd
 create mode 100644 lib/CPUs/JCpu/src/hallo_welt_uart_irom.vhdl
 create mode 100644 lib/CPUs/JCpu/src/hallo_welt_uart_irom_ld.vhdl
 create mode 100644 lib/CPUs/JCpu/src/hallo_welt_uart_xrom.vhdl
 create mode 100644 lib/CPUs/JCpu/src/hallo_welt_uart_xrom_ld.vhdl
 create mode 100644 lib/CPUs/JCpu/src/tb_cpu_embedded_with_uart.vhd

diff --git a/lib/CPUs/JCpu/src/cpu_embedded_with_uart.vhd b/lib/CPUs/JCpu/src/cpu_embedded_with_uart.vhd
new file mode 100644
index 0000000..d2d543e
--- /dev/null
+++ b/lib/CPUs/JCpu/src/cpu_embedded_with_uart.vhd
@@ -0,0 +1,229 @@
+-------------------------------------------------------------------------
+-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
+-- This file: cpu_embedded using cpu_core and rom
+--
+-- Copyright (C) 2007 J. Ahrensfeld
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
+--
+-- For questions and ideas, please contact the author at jens@jayfield.org
+--
+--------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.numeric_std.ALL;
+
+use work.cpu_pkg.all;
+use work.uart_types.all;
+
+entity cpu_embedded_with_uart is
+	Port 
+	(
+		rst			: in  STD_LOGIC;
+		clk			: in  STD_LOGIC;
+		ce			: in  STD_LOGIC;
+		int_in		: in  STD_LOGIC;
+		int_ack		: out STD_LOGIC;
+		xmem_we		: out STD_LOGIC;
+		xmem_re		: out STD_LOGIC;
+		xmem_din	: in  unsigned (DMEM_DATA_WIDTH-1 downto 0);
+		xmem_dout	: out unsigned (DMEM_DATA_WIDTH-1 downto 0);
+		xmem_addr	: out unsigned (DMEM_ADDR_WIDTH-1 downto 0);
+		io_sel		: out STD_LOGIC;
+		uart_tx		: out STD_LOGIC;
+		uart_rx		: in  STD_LOGIC
+	);
+end cpu_embedded_with_uart;
+
+architecture rtl of cpu_embedded_with_uart is
+
+	COMPONENT cpu
+	Port 
+	(
+		rst			: in  STD_LOGIC;
+		clk			: in  STD_LOGIC;
+		ce			: in  STD_LOGIC;
+		int_in		: in  STD_LOGIC;
+		int_ack		: out STD_LOGIC;
+		xmem_we		: out STD_LOGIC;
+		xmem_re		: out STD_LOGIC;
+		instr_din	: in  unsigned (IMEM_DATA_WIDTH-1 downto 0);
+		instr_addr	: out unsigned (IMEM_ADDR_WIDTH-1 downto 0);
+		xmem_din	: in  unsigned (DMEM_DATA_WIDTH-1 downto 0);
+		xmem_dout	: out unsigned (DMEM_DATA_WIDTH-1 downto 0);
+		xmem_addr	: out unsigned (DMEM_DATA_WIDTH-1 downto 0);
+		io_sel		: out STD_LOGIC
+	);
+	END COMPONENT;
+
+	signal cpu_irom_addr : inst_addr_t;
+	signal cpu_xmem_addr	: dmem_addr_t;
+	signal cpu_xmem_din		: dmem_data_t;
+	signal cpu_xmem_dout	: dmem_data_t;
+	signal cpu_io_sel		: STD_LOGIC;
+	signal cpu_xmem_we		: STD_LOGIC;
+	signal cpu_xmem_re		: STD_LOGIC;
+	
+	
+	COMPONENT irom
+		Port 
+		(
+			clk			: in  STD_LOGIC;
+			ce			: in  STD_LOGIC;
+			addr		: in  inst_addr_t;
+			dout		: out inst_t
+		);
+	END COMPONENT;
+
+	signal irom_data : inst_t;
+
+
+	COMPONENT xrom
+		Port 
+		(
+			clk			: in  STD_LOGIC;
+			ce			: in  STD_LOGIC;
+			addr		: in  dmem_addr_t;
+			dout		: out dmem_data_t
+		);
+	END COMPONENT;
+
+	signal rom_xmem_dout	: dmem_data_t;
+	signal reg_xmem_dout 	: dmem_data_t;
+	
+	signal uart_tx_we	: STD_LOGIC;
+	signal uart_rx_re	: STD_LOGIC;
+	signal uart_tx_din	: unsigned(7 downto 0);
+	signal uart_rx_dout	: unsigned(7 downto 0);
+	signal uart_ctrl	: ctrl_t;
+	signal uart_status	: status_t;
+	
+	COMPONENT uart
+	Generic 
+	(
+		fifo_depth_bits	: integer := 4
+	);
+	Port
+	(
+		clk			: in  STD_LOGIC;
+		rst			: in  STD_LOGIC;
+		we			: in  STD_LOGIC;
+		re			: in  STD_LOGIC;
+		din			: in  unsigned(7 downto 0);
+		dout		: out unsigned(7 downto 0);
+		ser_rx		: in  std_logic;
+		ser_tx		: out std_logic;
+		ctrl		: in  ctrl_t;
+		status		: out status_t
+	);
+	END COMPONENT;
+
+begin
+
+	cpu_xmem_din	<= rom_xmem_dout when cpu_io_sel = '0' else reg_xmem_dout;
+	
+inst_cpu: cpu
+	PORT MAP
+	(
+		rst => rst,
+		clk => clk,
+		ce => ce,
+		int_in => int_in,
+		int_ack => int_ack,
+		xmem_we => cpu_xmem_we,
+		xmem_re => cpu_xmem_re,
+		instr_din => irom_data,
+		instr_addr => cpu_irom_addr,
+		xmem_din => cpu_xmem_din,
+		xmem_dout => cpu_xmem_dout,
+		xmem_addr => cpu_xmem_addr,
+		io_sel => cpu_io_sel
+	);
+
+inst_irom: irom
+	PORT MAP
+	(
+		clk			=> clk,
+		ce			=> ce,
+		addr		=> cpu_irom_addr,
+		dout 		=> irom_data
+	);
+
+	inst_xrom: entity work.xrom
+	PORT MAP
+	(
+		clk			=> clk,
+		ce			=> ce,
+		addr		=> cpu_xmem_addr,
+		dout 		=> rom_xmem_dout
+	);
+
+inst_uart : uart
+	PORT MAP
+	(
+		rst					=> rst,
+		clk					=> clk,
+		we					=> uart_tx_we,
+		re					=> uart_rx_re,
+		din					=> uart_tx_din,
+		dout				=> uart_rx_dout,
+		ser_tx				=> uart_tx,
+		ser_rx				=> uart_rx,
+		ctrl				=> uart_ctrl,
+		status				=> uart_status
+	);
+
+	uart_tx_din <= cpu_xmem_dout;
+
+cpu_reg_read:
+	process(clk)
+	variable reg : dmem_data_t;
+	begin
+		if rising_edge(clk) then
+			uart_rx_re <= '0';
+			case cpu_xmem_addr is
+				when X"02" =>
+					uart_rx_re <= '1';
+					reg_xmem_dout <= uart_rx_dout;
+				when X"06" =>
+					reg_xmem_dout <= '0' & '0' & '0' & uart_status.rx_present & '0' & uart_status.tx_complete & uart_status.tx_full & uart_status.tx_empty;
+
+			when others => null;
+
+			end case;
+		end if;	
+		
+	end process;
+
+------------------------------------------------------------------
+cpu_reg_write:
+	process(clk)
+	begin
+		if rising_edge(clk) then
+			uart_tx_we <= '0';
+			if cpu_xmem_we = '1' then	
+				if cpu_io_sel = '1' then
+					case cpu_xmem_addr is
+						when X"02" =>
+							uart_tx_we <= '1';
+						when others => null;
+					end case;
+				end if;	
+			end if;	
+		end if;	
+	end process;
+
+end rtl;
+
diff --git a/lib/CPUs/JCpu/src/hallo_welt_uart_irom.vhdl b/lib/CPUs/JCpu/src/hallo_welt_uart_irom.vhdl
new file mode 100644
index 0000000..2411144
--- /dev/null
+++ b/lib/CPUs/JCpu/src/hallo_welt_uart_irom.vhdl
@@ -0,0 +1,184 @@
+-------------------------------------------------------------------------
+-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
+-- This file: The ROM file for use in your VHDL design
+--
+-- Copyright (C) 2007 J. Ahrensfeld
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
+--
+-- For questions and ideas, please contact the author at jens@jayfield.org
+--
+--------------------------------------------------------------------------
+
+LIBRARY ieee;
+use IEEE.STD_LOGIC_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+library work;
+use work.cpu_pkg.all;
+
+-- JASM_ROM_INSERT_HERE
+ENTITY irom IS
+	Port (
+	clk			: in  STD_LOGIC;
+	ce			: in  STD_LOGIC;
+	addr		: in  inst_addr_t;
+	dout		: out inst_t
+	);
+END irom;
+
+ARCHITECTURE hallo_welt_uart OF irom IS 
+
+	type imem_rom_t is array (0 to 122) of inst_t;
+
+	-- Assembled from hallo_welt_uart.jsm
+	constant imem_rom : imem_rom_t :=
+	(
+		"110000" & X"002", -- 0x000: JMP 0x002
+		"111111" & X"000", -- 0x001: RETI
+		"101000" & X"020", -- 0x002: XIN R00, (0x02)
+		"111011" & X"027", -- 0x003: CALL 0x027
+		"111011" & X"037", -- 0x004: CALL 0x037
+		"000010" & X"010", -- 0x005: MOV R00, R01
+		"111011" & X"037", -- 0x006: CALL 0x037
+		"000011" & X"001", -- 0x007: MOV R01, 0x00
+		"111011" & X"02E", -- 0x008: CALL 0x02E
+		"000011" & X"031", -- 0x009: MOV R01, 0x03
+		"111011" & X"02E", -- 0x00A: CALL 0x02E
+		"101001" & X"000", -- 0x00B: CIN R00, (0x00)
+		"010001" & X"300", -- 0x00C: ADD R00, 0x30
+		"111011" & X"037", -- 0x00D: CALL 0x037
+		"000011" & X"001", -- 0x00E: MOV R01, 0x00
+		"111011" & X"02E", -- 0x00F: CALL 0x02E
+		"000011" & X"0D1", -- 0x010: MOV R01, 0x0D
+		"111011" & X"02E", -- 0x011: CALL 0x02E
+		"000011" & X"161", -- 0x012: MOV R01, 0x16
+		"111011" & X"02E", -- 0x013: CALL 0x02E
+		"000011" & X"A0F", -- 0x014: MOV R15, 0xA0
+		"001111" & X"00F", -- 0x015: TST R15
+		"110001" & X"020", -- 0x016: JZ 0x020
+		"010101" & X"01F", -- 0x017: DEC R15
+		"000011" & X"301", -- 0x018: MOV R01, 0x30
+		"001111" & X"3A1", -- 0x019: CMP R01, 0x3A
+		"111001" & X"01F", -- 0x01A: JEQ 0x01F
+		"000010" & X"010", -- 0x01B: MOV R00, R01
+		"010001" & X"011", -- 0x01C: INC R01
+		"111011" & X"037", -- 0x01D: CALL 0x037
+		"110000" & X"019", -- 0x01E: JMP 0x019
+		"110000" & X"015", -- 0x01F: JMP 0x015
+		"110000" & X"009", -- 0x020: JMP 0x009
+		"011001" & X"0F0", -- 0x021: AND R00, 0x0F
+		"001111" & X"0A0", -- 0x022: CMP R00, 0x0A
+		"110101" & X"025", -- 0x023: JLT 0x025
+		"010001" & X"070", -- 0x024: ADD R00, 0x07
+		"010001" & X"300", -- 0x025: ADD R00, 0x30
+		"111110" & X"000", -- 0x026: RET
+		"111100" & X"000", -- 0x027: PUSH R00
+		"111011" & X"021", -- 0x028: CALL 0x021
+		"000010" & X"001", -- 0x029: MOV R01, R00
+		"111101" & X"000", -- 0x02A: POP R00
+		"101010" & X"000", -- 0x02B: SWAP R00
+		"111011" & X"021", -- 0x02C: CALL 0x021
+		"111110" & X"000", -- 0x02D: RET
+		"111100" & X"000", -- 0x02E: PUSH R00
+		"000100" & X"010", -- 0x02F: MOVX R00, (R01)
+		"010001" & X"011", -- 0x030: INC R01
+		"001111" & X"000", -- 0x031: TST R00
+		"110001" & X"035", -- 0x032: JZ 0x035
+		"111011" & X"037", -- 0x033: CALL 0x037
+		"110000" & X"02F", -- 0x034: JMP 0x02F
+		"111101" & X"000", -- 0x035: POP R00
+		"111110" & X"000", -- 0x036: RET
+		"110000" & X"038", -- 0x037: JMP 0x038
+		"111100" & X"001", -- 0x038: PUSH R01
+		"101000" & X"061", -- 0x039: XIN R01, (0x06)
+		"011001" & X"021", -- 0x03A: AND R01, 0x02
+		"110010" & X"039", -- 0x03B: JNZ 0x039
+		"100100" & X"020", -- 0x03C: XOUT (0x02), R00
+		"111101" & X"001", -- 0x03D: POP R01
+		"111110" & X"000", -- 0x03E: RET
+		"111100" & X"001", -- 0x03F: PUSH R01
+		"101000" & X"061", -- 0x040: XIN R01, (0x06)
+		"011001" & X"101", -- 0x041: AND R01, 0x10
+		"110010" & X"040", -- 0x042: JNZ 0x040
+		"101000" & X"020", -- 0x043: XIN R00, (0x02)
+		"111101" & X"001", -- 0x044: POP R01
+		"111110" & X"000", -- 0x045: RET
+		"111100" & X"00F", -- 0x046: PUSH R15
+		"000011" & X"0AF", -- 0x047: MOV R15, 0x0A
+		"111011" & X"04D", -- 0x048: CALL 0x04D
+		"010101" & X"01F", -- 0x049: DEC R15
+		"110010" & X"048", -- 0x04A: JNZ 0x048
+		"111101" & X"00F", -- 0x04B: POP R15
+		"111110" & X"000", -- 0x04C: RET
+		"111100" & X"00F", -- 0x04D: PUSH R15
+		"000011" & X"0AF", -- 0x04E: MOV R15, 0x0A
+		"111011" & X"054", -- 0x04F: CALL 0x054
+		"010101" & X"01F", -- 0x050: DEC R15
+		"110010" & X"04F", -- 0x051: JNZ 0x04F
+		"111101" & X"00F", -- 0x052: POP R15
+		"111110" & X"000", -- 0x053: RET
+		"111100" & X"00F", -- 0x054: PUSH R15
+		"000011" & X"0AF", -- 0x055: MOV R15, 0x0A
+		"111011" & X"05B", -- 0x056: CALL 0x05B
+		"010101" & X"01F", -- 0x057: DEC R15
+		"110010" & X"056", -- 0x058: JNZ 0x056
+		"111101" & X"00F", -- 0x059: POP R15
+		"111110" & X"000", -- 0x05A: RET
+		"111100" & X"00F", -- 0x05B: PUSH R15
+		"000011" & X"0AF", -- 0x05C: MOV R15, 0x0A
+		"111011" & X"062", -- 0x05D: CALL 0x062
+		"010101" & X"01F", -- 0x05E: DEC R15
+		"110010" & X"05D", -- 0x05F: JNZ 0x05D
+		"111101" & X"00F", -- 0x060: POP R15
+		"111110" & X"000", -- 0x061: RET
+		"111100" & X"00F", -- 0x062: PUSH R15
+		"000011" & X"0AF", -- 0x063: MOV R15, 0x0A
+		"111011" & X"069", -- 0x064: CALL 0x069
+		"010101" & X"01F", -- 0x065: DEC R15
+		"110010" & X"064", -- 0x066: JNZ 0x064
+		"111101" & X"00F", -- 0x067: POP R15
+		"111110" & X"000", -- 0x068: RET
+		"111100" & X"00F", -- 0x069: PUSH R15
+		"000011" & X"63F", -- 0x06A: MOV R15, 0x63
+		"000000" & X"000", -- 0x06B: NOP
+		"000000" & X"000", -- 0x06C: NOP
+		"000000" & X"000", -- 0x06D: NOP
+		"010101" & X"01F", -- 0x06E: DEC R15
+		"110010" & X"06B", -- 0x06F: JNZ 0x06B
+		"111101" & X"00F", -- 0x070: POP R15
+		"111110" & X"000", -- 0x071: RET
+		"111100" & X"00F", -- 0x072: PUSH R15
+		"000011" & X"09F", -- 0x073: MOV R15, 0x09
+		"000000" & X"000", -- 0x074: NOP
+		"000000" & X"000", -- 0x075: NOP
+		"000000" & X"000", -- 0x076: NOP
+		"010101" & X"01F", -- 0x077: DEC R15
+		"110010" & X"074", -- 0x078: JNZ 0x074
+		"111101" & X"00F", -- 0x079: POP R15
+		"111110" & X"000"  -- 0x07A: RET
+	);
+
+begin
+
+PROM_READ:
+	process(clk, ce)
+	begin
+		if rising_edge(clk) and ce = '1' then
+			dout <= imem_rom(to_integer(addr));
+		end if;
+	end process;
+
+end hallo_welt_uart;
+
diff --git a/lib/CPUs/JCpu/src/hallo_welt_uart_irom_ld.vhdl b/lib/CPUs/JCpu/src/hallo_welt_uart_irom_ld.vhdl
new file mode 100644
index 0000000..bb9ecd7
--- /dev/null
+++ b/lib/CPUs/JCpu/src/hallo_welt_uart_irom_ld.vhdl
@@ -0,0 +1,1181 @@
+-------------------------------------------------------------------------
+-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
+-- This file: loadable ROM
+--
+-- Copyright (C) 2007 J. Ahrensfeld
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
+--
+-- For questions and ideas, please contact the author at jens@jayfield.org
+--
+--------------------------------------------------------------------------
+
+LIBRARY ieee;
+use IEEE.STD_LOGIC_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+library UNISIM;
+use UNISIM.VComponents.all;
+
+library work;
+use work.cpu_pkg.all;
+
+ENTITY irom IS
+	Port (
+		clk			: in  STD_LOGIC;
+		ce			: in  STD_LOGIC;
+		addr		: in  inst_addr_t;
+		dout		: out inst_t
+	);
+	
+END irom;
+
+ARCHITECTURE loadable OF irom IS 
+
+	-- JASM_ROM_INSERT_HERE
+
+	-- Assembled from hallo_welt_uart.jsm
+	type imem_rom_t is array (0 to 1023) of inst_t;
+	signal imem_rom : imem_rom_t :=
+	(
+		"110000" & X"002", -- 0x000: JMP 0x002
+		"111111" & X"000", -- 0x001: RETI
+		"101000" & X"020", -- 0x002: XIN R00, (0x02)
+		"111011" & X"027", -- 0x003: CALL 0x027
+		"111011" & X"037", -- 0x004: CALL 0x037
+		"000010" & X"010", -- 0x005: MOV R00, R01
+		"111011" & X"037", -- 0x006: CALL 0x037
+		"000011" & X"001", -- 0x007: MOV R01, 0x00
+		"111011" & X"02E", -- 0x008: CALL 0x02E
+		"000011" & X"031", -- 0x009: MOV R01, 0x03
+		"111011" & X"02E", -- 0x00A: CALL 0x02E
+		"101001" & X"000", -- 0x00B: CIN R00, (0x00)
+		"010001" & X"300", -- 0x00C: ADD R00, 0x30
+		"111011" & X"037", -- 0x00D: CALL 0x037
+		"000011" & X"001", -- 0x00E: MOV R01, 0x00
+		"111011" & X"02E", -- 0x00F: CALL 0x02E
+		"000011" & X"0D1", -- 0x010: MOV R01, 0x0D
+		"111011" & X"02E", -- 0x011: CALL 0x02E
+		"000011" & X"161", -- 0x012: MOV R01, 0x16
+		"111011" & X"02E", -- 0x013: CALL 0x02E
+		"000011" & X"A0F", -- 0x014: MOV R15, 0xA0
+		"001111" & X"00F", -- 0x015: TST R15
+		"110001" & X"020", -- 0x016: JZ 0x020
+		"010101" & X"01F", -- 0x017: DEC R15
+		"000011" & X"301", -- 0x018: MOV R01, 0x30
+		"001111" & X"3A1", -- 0x019: CMP R01, 0x3A
+		"111001" & X"01F", -- 0x01A: JEQ 0x01F
+		"000010" & X"010", -- 0x01B: MOV R00, R01
+		"010001" & X"011", -- 0x01C: INC R01
+		"111011" & X"037", -- 0x01D: CALL 0x037
+		"110000" & X"019", -- 0x01E: JMP 0x019
+		"110000" & X"015", -- 0x01F: JMP 0x015
+		"110000" & X"009", -- 0x020: JMP 0x009
+		"011001" & X"0F0", -- 0x021: AND R00, 0x0F
+		"001111" & X"0A0", -- 0x022: CMP R00, 0x0A
+		"110101" & X"025", -- 0x023: JLT 0x025
+		"010001" & X"070", -- 0x024: ADD R00, 0x07
+		"010001" & X"300", -- 0x025: ADD R00, 0x30
+		"111110" & X"000", -- 0x026: RET
+		"111100" & X"000", -- 0x027: PUSH R00
+		"111011" & X"021", -- 0x028: CALL 0x021
+		"000010" & X"001", -- 0x029: MOV R01, R00
+		"111101" & X"000", -- 0x02A: POP R00
+		"101010" & X"000", -- 0x02B: SWAP R00
+		"111011" & X"021", -- 0x02C: CALL 0x021
+		"111110" & X"000", -- 0x02D: RET
+		"111100" & X"000", -- 0x02E: PUSH R00
+		"000100" & X"010", -- 0x02F: MOVX R00, (R01)
+		"010001" & X"011", -- 0x030: INC R01
+		"001111" & X"000", -- 0x031: TST R00
+		"110001" & X"035", -- 0x032: JZ 0x035
+		"111011" & X"037", -- 0x033: CALL 0x037
+		"110000" & X"02F", -- 0x034: JMP 0x02F
+		"111101" & X"000", -- 0x035: POP R00
+		"111110" & X"000", -- 0x036: RET
+		"110000" & X"038", -- 0x037: JMP 0x038
+		"111100" & X"001", -- 0x038: PUSH R01
+		"101000" & X"061", -- 0x039: XIN R01, (0x06)
+		"011001" & X"021", -- 0x03A: AND R01, 0x02
+		"110010" & X"039", -- 0x03B: JNZ 0x039
+		"100100" & X"020", -- 0x03C: XOUT (0x02), R00
+		"111101" & X"001", -- 0x03D: POP R01
+		"111110" & X"000", -- 0x03E: RET
+		"111100" & X"001", -- 0x03F: PUSH R01
+		"101000" & X"061", -- 0x040: XIN R01, (0x06)
+		"011001" & X"101", -- 0x041: AND R01, 0x10
+		"110010" & X"040", -- 0x042: JNZ 0x040
+		"101000" & X"020", -- 0x043: XIN R00, (0x02)
+		"111101" & X"001", -- 0x044: POP R01
+		"111110" & X"000", -- 0x045: RET
+		"111100" & X"00F", -- 0x046: PUSH R15
+		"000011" & X"0AF", -- 0x047: MOV R15, 0x0A
+		"111011" & X"04D", -- 0x048: CALL 0x04D
+		"010101" & X"01F", -- 0x049: DEC R15
+		"110010" & X"048", -- 0x04A: JNZ 0x048
+		"111101" & X"00F", -- 0x04B: POP R15
+		"111110" & X"000", -- 0x04C: RET
+		"111100" & X"00F", -- 0x04D: PUSH R15
+		"000011" & X"0AF", -- 0x04E: MOV R15, 0x0A
+		"111011" & X"054", -- 0x04F: CALL 0x054
+		"010101" & X"01F", -- 0x050: DEC R15
+		"110010" & X"04F", -- 0x051: JNZ 0x04F
+		"111101" & X"00F", -- 0x052: POP R15
+		"111110" & X"000", -- 0x053: RET
+		"111100" & X"00F", -- 0x054: PUSH R15
+		"000011" & X"0AF", -- 0x055: MOV R15, 0x0A
+		"111011" & X"05B", -- 0x056: CALL 0x05B
+		"010101" & X"01F", -- 0x057: DEC R15
+		"110010" & X"056", -- 0x058: JNZ 0x056
+		"111101" & X"00F", -- 0x059: POP R15
+		"111110" & X"000", -- 0x05A: RET
+		"111100" & X"00F", -- 0x05B: PUSH R15
+		"000011" & X"0AF", -- 0x05C: MOV R15, 0x0A
+		"111011" & X"062", -- 0x05D: CALL 0x062
+		"010101" & X"01F", -- 0x05E: DEC R15
+		"110010" & X"05D", -- 0x05F: JNZ 0x05D
+		"111101" & X"00F", -- 0x060: POP R15
+		"111110" & X"000", -- 0x061: RET
+		"111100" & X"00F", -- 0x062: PUSH R15
+		"000011" & X"0AF", -- 0x063: MOV R15, 0x0A
+		"111011" & X"069", -- 0x064: CALL 0x069
+		"010101" & X"01F", -- 0x065: DEC R15
+		"110010" & X"064", -- 0x066: JNZ 0x064
+		"111101" & X"00F", -- 0x067: POP R15
+		"111110" & X"000", -- 0x068: RET
+		"111100" & X"00F", -- 0x069: PUSH R15
+		"000011" & X"63F", -- 0x06A: MOV R15, 0x63
+		"000000" & X"000", -- 0x06B: NOP
+		"000000" & X"000", -- 0x06C: NOP
+		"000000" & X"000", -- 0x06D: NOP
+		"010101" & X"01F", -- 0x06E: DEC R15
+		"110010" & X"06B", -- 0x06F: JNZ 0x06B
+		"111101" & X"00F", -- 0x070: POP R15
+		"111110" & X"000", -- 0x071: RET
+		"111100" & X"00F", -- 0x072: PUSH R15
+		"000011" & X"09F", -- 0x073: MOV R15, 0x09
+		"000000" & X"000", -- 0x074: NOP
+		"000000" & X"000", -- 0x075: NOP
+		"000000" & X"000", -- 0x076: NOP
+		"010101" & X"01F", -- 0x077: DEC R15
+		"110010" & X"074", -- 0x078: JNZ 0x074
+		"111101" & X"00F", -- 0x079: POP R15
+		"111110" & X"000", -- 0x07A: RET
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000"
+	);
+
+	signal jtag_ld_clk		: STD_LOGIC;
+	signal jtag_ld_we		: STD_LOGIC;
+	signal jtag_ld_addr		: inst_addr_t;
+	signal jtag_ld_dout		: inst_t;
+	signal jtag_ld_din		: inst_t;
+	signal bs_rst, bs_sel, bs_shift, bs_tdi, bs_tdo : std_logic;
+	signal bs_capture, bs_clk0, bs_clk1, bs_update0, bs_update1 : std_logic;
+	signal user_regi, user_rego : unsigned (31 downto 0);
+	constant id : unsigned (31 downto 0) := X"BABE" & X"BEEF";
+
+begin
+
+--------------------------------------------------------------------------
+-- Virtex-4: JTAG Loader
+--------------------------------------------------------------------------
+	i00_BUFG : BUFG
+	port map
+	(
+		O => bs_clk1,
+        I => bs_clk0
+	);
+	
+	i01_BUFG : BUFG
+	port map
+	(
+		O => bs_update1,
+        I => bs_update0
+	);
+
+	BSCAN_VIRTEX4_inst1 : BSCAN_VIRTEX4 
+	generic map
+	(
+		JTAG_CHAIN => 1 -- Value to set BSCAN site of device. Possible values: (1,2,3 or 4)
+	)
+	port map 
+	(
+		CAPTURE => bs_capture, -- CAPTURE output from TAP controller
+		DRCK => bs_clk0,       -- Data register output for USER functions
+		RESET => bs_rst,       -- Reset output from TAP controller
+		SEL => bs_sel,         -- USER active output
+		SHIFT => bs_shift,     -- SHIFT output from TAP controller
+		TDI => bs_tdi,        -- TDI output from TAP controller
+		UPDATE => bs_update0,   -- UPDATE output from TAP controller
+		TDO => bs_tdo         -- Data input for USER function
+	);
+
+	jtag_ld_addr <= user_regi(user_regi'left downto user_regi'left-inst_addr_t'length+1);
+	jtag_ld_din <= user_regi(inst_t'length-1 downto 0);
+	jtag_ld_clk <= bs_update1;
+	jtag_ld_we <= bs_sel;
+	
+sipo:
+	process (bs_rst, bs_clk1, bs_tdi, bs_shift)
+	begin
+		if bs_rst = '1' then
+			user_regi <= (others => '0');
+		elsif rising_edge(bs_clk1) then
+			if bs_shift = '1' then
+				user_regi <= bs_tdi & user_regi(user_regi'left downto 1);
+			end if;
+		end if;
+	end process;	
+
+piso:
+	process (bs_rst, bs_clk1, bs_shift, user_rego)
+	begin
+		bs_tdo <= user_rego(0);
+		if bs_rst = '1' then
+			user_rego <= (others => '0');
+		elsif rising_edge(bs_clk1) then
+			if bs_shift = '1' then
+				user_rego <= user_rego(0) & user_rego(user_rego'left downto 1);
+			else
+				user_rego <= (user_rego'left downto inst_t'length => '0') & jtag_ld_dout;	
+--				user_rego <= id;	
+			end if;
+		end if;
+	end process;	
+	
+--------------------------------------------------------------------------
+-- ROM Read/Write
+--------------------------------------------------------------------------
+PROM_READ: 
+	process(clk, ce)
+	begin
+		if rising_edge(clk) and ce = '1' then
+			dout <= imem_rom(to_integer(addr));
+		end if;
+	end process;
+
+PROM_WRITE: 
+	process(jtag_ld_clk, jtag_ld_we)
+	begin
+		if rising_edge(jtag_ld_clk) then
+			if jtag_ld_we = '1' then
+				imem_rom(to_integer(jtag_ld_addr)) <= jtag_ld_din;
+			else	
+				jtag_ld_dout <= imem_rom(to_integer(jtag_ld_addr));
+			end if;
+		end if;	
+	end process;
+
+--------------------------------------------------------------------------
+end loadable;
diff --git a/lib/CPUs/JCpu/src/hallo_welt_uart_xrom.vhdl b/lib/CPUs/JCpu/src/hallo_welt_uart_xrom.vhdl
new file mode 100644
index 0000000..b5d5583
--- /dev/null
+++ b/lib/CPUs/JCpu/src/hallo_welt_uart_xrom.vhdl
@@ -0,0 +1,317 @@
+-------------------------------------------------------------------------
+-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
+-- This file: The ROM file for use in your VHDL design
+--
+-- Copyright (C) 2007 J. Ahrensfeld
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
+--
+-- For questions and ideas, please contact the author at jens@jayfield.org
+--
+--------------------------------------------------------------------------
+
+LIBRARY ieee;
+use IEEE.STD_LOGIC_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+library work;
+use work.cpu_pkg.all;
+
+-- JASM_ROM_INSERT_HERE
+ENTITY xrom IS
+	Port (
+	clk			: in  STD_LOGIC;
+	ce			: in  STD_LOGIC;
+	addr		: in  dmem_addr_t;
+	dout		: out dmem_data_t
+	);
+END xrom;
+
+ARCHITECTURE hallo_welt_uart OF xrom IS 
+
+	type xmem_rom_t is array (0 to 255) of dmem_data_t;
+
+	-- Assembled from hallo_welt_uart.jsm
+	constant xmem_rom : xmem_rom_t :=
+	(
+		X"0D", -- 0x00
+		X"0A", -- 0x01
+		X"00", -- 0x02
+		X"4A", -- 0x03
+		X"2D", -- 0x04
+		X"43", -- 0x05
+		X"50", -- 0x06
+		X"55", -- 0x07
+		X"20", -- 0x08
+		X"56", -- 0x09
+		X"31", -- 0x0A
+		X"2E", -- 0x0B
+		X"00", -- 0x0C
+		X"52", -- 0x0D
+		X"65", -- 0x0E
+		X"61", -- 0x0F
+		X"64", -- 0x10
+		X"79", -- 0x11
+		X"2E", -- 0x12
+		X"0D", -- 0x13
+		X"0A", -- 0x14
+		X"00", -- 0x15
+		X"4D", -- 0x16
+		X"69", -- 0x17
+		X"6D", -- 0x18
+		X"69", -- 0x19
+		X"20", -- 0x1A
+		X"69", -- 0x1B
+		X"73", -- 0x1C
+		X"74", -- 0x1D
+		X"20", -- 0x1E
+		X"65", -- 0x1F
+		X"69", -- 0x20
+		X"6E", -- 0x21
+		X"65", -- 0x22
+		X"20", -- 0x23
+		X"6C", -- 0x24
+		X"69", -- 0x25
+		X"65", -- 0x26
+		X"62", -- 0x27
+		X"65", -- 0x28
+		X"20", -- 0x29
+		X"4B", -- 0x2A
+		X"61", -- 0x2B
+		X"74", -- 0x2C
+		X"7A", -- 0x2D
+		X"65", -- 0x2E
+		X"20", -- 0x2F
+		X"21", -- 0x30
+		X"21", -- 0x31
+		X"21", -- 0x32
+		X"0D", -- 0x33
+		X"0A", -- 0x34
+		X"00", -- 0x35
+		X"00", -- 0x36
+		X"00", -- 0x37
+		X"00", -- 0x38
+		X"00", -- 0x39
+		X"00", -- 0x3A
+		X"00", -- 0x3B
+		X"00", -- 0x3C
+		X"00", -- 0x3D
+		X"00", -- 0x3E
+		X"00", -- 0x3F
+		X"00", -- 0x40
+		X"00", -- 0x41
+		X"00", -- 0x42
+		X"00", -- 0x43
+		X"00", -- 0x44
+		X"00", -- 0x45
+		X"00", -- 0x46
+		X"00", -- 0x47
+		X"00", -- 0x48
+		X"00", -- 0x49
+		X"00", -- 0x4A
+		X"00", -- 0x4B
+		X"00", -- 0x4C
+		X"00", -- 0x4D
+		X"00", -- 0x4E
+		X"00", -- 0x4F
+		X"00", -- 0x50
+		X"00", -- 0x51
+		X"00", -- 0x52
+		X"00", -- 0x53
+		X"00", -- 0x54
+		X"00", -- 0x55
+		X"00", -- 0x56
+		X"00", -- 0x57
+		X"00", -- 0x58
+		X"00", -- 0x59
+		X"00", -- 0x5A
+		X"00", -- 0x5B
+		X"00", -- 0x5C
+		X"00", -- 0x5D
+		X"00", -- 0x5E
+		X"00", -- 0x5F
+		X"00", -- 0x60
+		X"00", -- 0x61
+		X"00", -- 0x62
+		X"00", -- 0x63
+		X"00", -- 0x64
+		X"00", -- 0x65
+		X"00", -- 0x66
+		X"00", -- 0x67
+		X"00", -- 0x68
+		X"00", -- 0x69
+		X"00", -- 0x6A
+		X"00", -- 0x6B
+		X"00", -- 0x6C
+		X"00", -- 0x6D
+		X"00", -- 0x6E
+		X"00", -- 0x6F
+		X"00", -- 0x70
+		X"00", -- 0x71
+		X"00", -- 0x72
+		X"00", -- 0x73
+		X"00", -- 0x74
+		X"00", -- 0x75
+		X"00", -- 0x76
+		X"00", -- 0x77
+		X"00", -- 0x78
+		X"00", -- 0x79
+		X"00", -- 0x7A
+		X"00", -- 0x7B
+		X"00", -- 0x7C
+		X"00", -- 0x7D
+		X"00", -- 0x7E
+		X"00", -- 0x7F
+		X"00", -- 0x80
+		X"00", -- 0x81
+		X"00", -- 0x82
+		X"00", -- 0x83
+		X"00", -- 0x84
+		X"00", -- 0x85
+		X"00", -- 0x86
+		X"00", -- 0x87
+		X"00", -- 0x88
+		X"00", -- 0x89
+		X"00", -- 0x8A
+		X"00", -- 0x8B
+		X"00", -- 0x8C
+		X"00", -- 0x8D
+		X"00", -- 0x8E
+		X"00", -- 0x8F
+		X"00", -- 0x90
+		X"00", -- 0x91
+		X"00", -- 0x92
+		X"00", -- 0x93
+		X"00", -- 0x94
+		X"00", -- 0x95
+		X"00", -- 0x96
+		X"00", -- 0x97
+		X"00", -- 0x98
+		X"00", -- 0x99
+		X"00", -- 0x9A
+		X"00", -- 0x9B
+		X"00", -- 0x9C
+		X"00", -- 0x9D
+		X"00", -- 0x9E
+		X"00", -- 0x9F
+		X"00", -- 0xA0
+		X"00", -- 0xA1
+		X"00", -- 0xA2
+		X"00", -- 0xA3
+		X"00", -- 0xA4
+		X"00", -- 0xA5
+		X"00", -- 0xA6
+		X"00", -- 0xA7
+		X"00", -- 0xA8
+		X"00", -- 0xA9
+		X"00", -- 0xAA
+		X"00", -- 0xAB
+		X"00", -- 0xAC
+		X"00", -- 0xAD
+		X"00", -- 0xAE
+		X"00", -- 0xAF
+		X"00", -- 0xB0
+		X"00", -- 0xB1
+		X"00", -- 0xB2
+		X"00", -- 0xB3
+		X"00", -- 0xB4
+		X"00", -- 0xB5
+		X"00", -- 0xB6
+		X"00", -- 0xB7
+		X"00", -- 0xB8
+		X"00", -- 0xB9
+		X"00", -- 0xBA
+		X"00", -- 0xBB
+		X"00", -- 0xBC
+		X"00", -- 0xBD
+		X"00", -- 0xBE
+		X"00", -- 0xBF
+		X"00", -- 0xC0
+		X"00", -- 0xC1
+		X"00", -- 0xC2
+		X"00", -- 0xC3
+		X"00", -- 0xC4
+		X"00", -- 0xC5
+		X"00", -- 0xC6
+		X"00", -- 0xC7
+		X"00", -- 0xC8
+		X"00", -- 0xC9
+		X"00", -- 0xCA
+		X"00", -- 0xCB
+		X"00", -- 0xCC
+		X"00", -- 0xCD
+		X"00", -- 0xCE
+		X"00", -- 0xCF
+		X"00", -- 0xD0
+		X"00", -- 0xD1
+		X"00", -- 0xD2
+		X"00", -- 0xD3
+		X"00", -- 0xD4
+		X"00", -- 0xD5
+		X"00", -- 0xD6
+		X"00", -- 0xD7
+		X"00", -- 0xD8
+		X"00", -- 0xD9
+		X"00", -- 0xDA
+		X"00", -- 0xDB
+		X"00", -- 0xDC
+		X"00", -- 0xDD
+		X"00", -- 0xDE
+		X"00", -- 0xDF
+		X"00", -- 0xE0
+		X"00", -- 0xE1
+		X"00", -- 0xE2
+		X"00", -- 0xE3
+		X"00", -- 0xE4
+		X"00", -- 0xE5
+		X"00", -- 0xE6
+		X"00", -- 0xE7
+		X"00", -- 0xE8
+		X"00", -- 0xE9
+		X"00", -- 0xEA
+		X"00", -- 0xEB
+		X"00", -- 0xEC
+		X"00", -- 0xED
+		X"00", -- 0xEE
+		X"00", -- 0xEF
+		X"00", -- 0xF0
+		X"00", -- 0xF1
+		X"00", -- 0xF2
+		X"00", -- 0xF3
+		X"00", -- 0xF4
+		X"00", -- 0xF5
+		X"00", -- 0xF6
+		X"00", -- 0xF7
+		X"00", -- 0xF8
+		X"00", -- 0xF9
+		X"00", -- 0xFA
+		X"00", -- 0xFB
+		X"00", -- 0xFC
+		X"00", -- 0xFD
+		X"00", -- 0xFE
+		X"00"  -- 0xFF
+	);
+
+begin
+
+PROM_READ:
+	process(clk, ce)
+	begin
+		if rising_edge(clk) and ce = '1' then
+			dout <= xmem_rom(to_integer(addr));
+		end if;
+	end process;
+
+end hallo_welt_uart;
+
diff --git a/lib/CPUs/JCpu/src/hallo_welt_uart_xrom_ld.vhdl b/lib/CPUs/JCpu/src/hallo_welt_uart_xrom_ld.vhdl
new file mode 100644
index 0000000..e4b343a
--- /dev/null
+++ b/lib/CPUs/JCpu/src/hallo_welt_uart_xrom_ld.vhdl
@@ -0,0 +1,413 @@
+-------------------------------------------------------------------------
+-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
+-- This file: loadable ROM
+--
+-- Copyright (C) 2007 J. Ahrensfeld
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
+--
+-- For questions and ideas, please contact the author at jens@jayfield.org
+--
+--------------------------------------------------------------------------
+
+LIBRARY ieee;
+use IEEE.STD_LOGIC_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+library UNISIM;
+use UNISIM.VComponents.all;
+
+library work;
+use work.cpu_pkg.all;
+
+ENTITY xrom IS
+	Port (
+		clk			: in  STD_LOGIC;
+		ce			: in  STD_LOGIC;
+		addr		: in  dmem_addr_t;
+		dout		: out dmem_data_t
+	);
+	
+END xrom;
+
+ARCHITECTURE loadable OF xrom IS 
+
+	-- JASM_ROM_INSERT_HERE
+
+	-- Assembled from hallo_welt_uart.jsm
+	type xmem_rom_t is array (0 to 255) of dmem_data_t;
+	signal xmem_rom : xmem_rom_t :=
+	(
+		X"0D", -- 0x00
+		X"0A", -- 0x01
+		X"00", -- 0x02
+		X"4A", -- 0x03
+		X"2D", -- 0x04
+		X"43", -- 0x05
+		X"50", -- 0x06
+		X"55", -- 0x07
+		X"20", -- 0x08
+		X"56", -- 0x09
+		X"31", -- 0x0A
+		X"2E", -- 0x0B
+		X"00", -- 0x0C
+		X"52", -- 0x0D
+		X"65", -- 0x0E
+		X"61", -- 0x0F
+		X"64", -- 0x10
+		X"79", -- 0x11
+		X"2E", -- 0x12
+		X"0D", -- 0x13
+		X"0A", -- 0x14
+		X"00", -- 0x15
+		X"4D", -- 0x16
+		X"69", -- 0x17
+		X"6D", -- 0x18
+		X"69", -- 0x19
+		X"20", -- 0x1A
+		X"69", -- 0x1B
+		X"73", -- 0x1C
+		X"74", -- 0x1D
+		X"20", -- 0x1E
+		X"65", -- 0x1F
+		X"69", -- 0x20
+		X"6E", -- 0x21
+		X"65", -- 0x22
+		X"20", -- 0x23
+		X"6C", -- 0x24
+		X"69", -- 0x25
+		X"65", -- 0x26
+		X"62", -- 0x27
+		X"65", -- 0x28
+		X"20", -- 0x29
+		X"4B", -- 0x2A
+		X"61", -- 0x2B
+		X"74", -- 0x2C
+		X"7A", -- 0x2D
+		X"65", -- 0x2E
+		X"20", -- 0x2F
+		X"21", -- 0x30
+		X"21", -- 0x31
+		X"21", -- 0x32
+		X"0D", -- 0x33
+		X"0A", -- 0x34
+		X"00", -- 0x35
+		X"00", -- 0x36
+		X"00", -- 0x37
+		X"00", -- 0x38
+		X"00", -- 0x39
+		X"00", -- 0x3A
+		X"00", -- 0x3B
+		X"00", -- 0x3C
+		X"00", -- 0x3D
+		X"00", -- 0x3E
+		X"00", -- 0x3F
+		X"00", -- 0x40
+		X"00", -- 0x41
+		X"00", -- 0x42
+		X"00", -- 0x43
+		X"00", -- 0x44
+		X"00", -- 0x45
+		X"00", -- 0x46
+		X"00", -- 0x47
+		X"00", -- 0x48
+		X"00", -- 0x49
+		X"00", -- 0x4A
+		X"00", -- 0x4B
+		X"00", -- 0x4C
+		X"00", -- 0x4D
+		X"00", -- 0x4E
+		X"00", -- 0x4F
+		X"00", -- 0x50
+		X"00", -- 0x51
+		X"00", -- 0x52
+		X"00", -- 0x53
+		X"00", -- 0x54
+		X"00", -- 0x55
+		X"00", -- 0x56
+		X"00", -- 0x57
+		X"00", -- 0x58
+		X"00", -- 0x59
+		X"00", -- 0x5A
+		X"00", -- 0x5B
+		X"00", -- 0x5C
+		X"00", -- 0x5D
+		X"00", -- 0x5E
+		X"00", -- 0x5F
+		X"00", -- 0x60
+		X"00", -- 0x61
+		X"00", -- 0x62
+		X"00", -- 0x63
+		X"00", -- 0x64
+		X"00", -- 0x65
+		X"00", -- 0x66
+		X"00", -- 0x67
+		X"00", -- 0x68
+		X"00", -- 0x69
+		X"00", -- 0x6A
+		X"00", -- 0x6B
+		X"00", -- 0x6C
+		X"00", -- 0x6D
+		X"00", -- 0x6E
+		X"00", -- 0x6F
+		X"00", -- 0x70
+		X"00", -- 0x71
+		X"00", -- 0x72
+		X"00", -- 0x73
+		X"00", -- 0x74
+		X"00", -- 0x75
+		X"00", -- 0x76
+		X"00", -- 0x77
+		X"00", -- 0x78
+		X"00", -- 0x79
+		X"00", -- 0x7A
+		X"00", -- 0x7B
+		X"00", -- 0x7C
+		X"00", -- 0x7D
+		X"00", -- 0x7E
+		X"00", -- 0x7F
+		X"00", -- 0x80
+		X"00", -- 0x81
+		X"00", -- 0x82
+		X"00", -- 0x83
+		X"00", -- 0x84
+		X"00", -- 0x85
+		X"00", -- 0x86
+		X"00", -- 0x87
+		X"00", -- 0x88
+		X"00", -- 0x89
+		X"00", -- 0x8A
+		X"00", -- 0x8B
+		X"00", -- 0x8C
+		X"00", -- 0x8D
+		X"00", -- 0x8E
+		X"00", -- 0x8F
+		X"00", -- 0x90
+		X"00", -- 0x91
+		X"00", -- 0x92
+		X"00", -- 0x93
+		X"00", -- 0x94
+		X"00", -- 0x95
+		X"00", -- 0x96
+		X"00", -- 0x97
+		X"00", -- 0x98
+		X"00", -- 0x99
+		X"00", -- 0x9A
+		X"00", -- 0x9B
+		X"00", -- 0x9C
+		X"00", -- 0x9D
+		X"00", -- 0x9E
+		X"00", -- 0x9F
+		X"00", -- 0xA0
+		X"00", -- 0xA1
+		X"00", -- 0xA2
+		X"00", -- 0xA3
+		X"00", -- 0xA4
+		X"00", -- 0xA5
+		X"00", -- 0xA6
+		X"00", -- 0xA7
+		X"00", -- 0xA8
+		X"00", -- 0xA9
+		X"00", -- 0xAA
+		X"00", -- 0xAB
+		X"00", -- 0xAC
+		X"00", -- 0xAD
+		X"00", -- 0xAE
+		X"00", -- 0xAF
+		X"00", -- 0xB0
+		X"00", -- 0xB1
+		X"00", -- 0xB2
+		X"00", -- 0xB3
+		X"00", -- 0xB4
+		X"00", -- 0xB5
+		X"00", -- 0xB6
+		X"00", -- 0xB7
+		X"00", -- 0xB8
+		X"00", -- 0xB9
+		X"00", -- 0xBA
+		X"00", -- 0xBB
+		X"00", -- 0xBC
+		X"00", -- 0xBD
+		X"00", -- 0xBE
+		X"00", -- 0xBF
+		X"00", -- 0xC0
+		X"00", -- 0xC1
+		X"00", -- 0xC2
+		X"00", -- 0xC3
+		X"00", -- 0xC4
+		X"00", -- 0xC5
+		X"00", -- 0xC6
+		X"00", -- 0xC7
+		X"00", -- 0xC8
+		X"00", -- 0xC9
+		X"00", -- 0xCA
+		X"00", -- 0xCB
+		X"00", -- 0xCC
+		X"00", -- 0xCD
+		X"00", -- 0xCE
+		X"00", -- 0xCF
+		X"00", -- 0xD0
+		X"00", -- 0xD1
+		X"00", -- 0xD2
+		X"00", -- 0xD3
+		X"00", -- 0xD4
+		X"00", -- 0xD5
+		X"00", -- 0xD6
+		X"00", -- 0xD7
+		X"00", -- 0xD8
+		X"00", -- 0xD9
+		X"00", -- 0xDA
+		X"00", -- 0xDB
+		X"00", -- 0xDC
+		X"00", -- 0xDD
+		X"00", -- 0xDE
+		X"00", -- 0xDF
+		X"00", -- 0xE0
+		X"00", -- 0xE1
+		X"00", -- 0xE2
+		X"00", -- 0xE3
+		X"00", -- 0xE4
+		X"00", -- 0xE5
+		X"00", -- 0xE6
+		X"00", -- 0xE7
+		X"00", -- 0xE8
+		X"00", -- 0xE9
+		X"00", -- 0xEA
+		X"00", -- 0xEB
+		X"00", -- 0xEC
+		X"00", -- 0xED
+		X"00", -- 0xEE
+		X"00", -- 0xEF
+		X"00", -- 0xF0
+		X"00", -- 0xF1
+		X"00", -- 0xF2
+		X"00", -- 0xF3
+		X"00", -- 0xF4
+		X"00", -- 0xF5
+		X"00", -- 0xF6
+		X"00", -- 0xF7
+		X"00", -- 0xF8
+		X"00", -- 0xF9
+		X"00", -- 0xFA
+		X"00", -- 0xFB
+		X"00", -- 0xFC
+		X"00", -- 0xFD
+		X"00", -- 0xFE
+		X"00"  -- 0xFF
+	);
+
+	signal jtag_ld_clk		: STD_LOGIC;
+	signal jtag_ld_we		: STD_LOGIC;
+	signal jtag_ld_addr		: dmem_addr_t;
+	signal jtag_ld_dout		: dmem_data_t;
+	signal jtag_ld_din		: dmem_data_t;
+	signal bs_rst, bs_sel, bs_shift, bs_tdi, bs_tdo : std_logic;
+	signal bs_capture, bs_clk0, bs_clk1, bs_update0, bs_update1 : std_logic;
+	signal user_regi, user_rego : unsigned (15 downto 0);
+	constant id : unsigned (15 downto 0) := X"BEEF";
+
+begin
+
+--------------------------------------------------------------------------
+-- Virtex-4: JTAG Loader
+--------------------------------------------------------------------------
+	i00_BUFG : BUFG
+	port map
+	(
+		O => bs_clk1,
+        I => bs_clk0
+	);
+	
+	i01_BUFG : BUFG
+	port map
+	(
+		O => bs_update1,
+        I => bs_update0
+	);
+
+	BSCAN_VIRTEX4_inst2 : BSCAN_VIRTEX4 
+	generic map
+	(
+		JTAG_CHAIN => 2 -- Value to set BSCAN site of device. Possible values: (1,2,3 or 4)
+	)
+	port map 
+	(
+		CAPTURE => bs_capture, -- CAPTURE output from TAP controller
+		DRCK => bs_clk0,       -- Data register output for USER functions
+		RESET => bs_rst,       -- Reset output from TAP controller
+		SEL => bs_sel,         -- USER active output
+		SHIFT => bs_shift,     -- SHIFT output from TAP controller
+		TDI => bs_tdi,        -- TDI output from TAP controller
+		UPDATE => bs_update0,   -- UPDATE output from TAP controller
+		TDO => bs_tdo         -- Data input for USER function
+	);
+
+	jtag_ld_addr <= user_regi(user_regi'left downto user_regi'left-dmem_data_t'length+1);
+	jtag_ld_din <= user_regi(dmem_data_t'left downto 0);
+	jtag_ld_clk <= bs_update1;
+	jtag_ld_we <= bs_sel;
+	
+sipo:
+	process (bs_rst, bs_clk1, bs_tdi, bs_shift)
+	begin
+		if bs_rst = '1' then
+			user_regi <= (others => '0');
+		elsif rising_edge(bs_clk1) then
+			if bs_shift = '1' then
+				user_regi <= bs_tdi & user_regi(user_regi'left downto 1);
+			end if;
+		end if;
+	end process;	
+
+piso:
+	process (bs_rst, bs_clk1, bs_shift, user_rego)
+	begin
+		bs_tdo <= user_rego(0);
+		if bs_rst = '1' then
+			user_rego <= (others => '0');
+		elsif rising_edge(bs_clk1) then
+			if bs_shift = '1' then
+				user_rego <= user_rego(0) & user_rego(user_rego'left downto 1);
+			else
+				user_rego <= (user_rego'left downto dmem_data_t'length => '0') & jtag_ld_dout;	
+--				user_rego <= id;	
+			end if;
+		end if;
+	end process;	
+	
+--------------------------------------------------------------------------
+-- ROM Read/Write
+--------------------------------------------------------------------------
+PROM_READ: 
+	process(clk, ce)
+	begin
+		if rising_edge(clk) and ce = '1' then
+			dout <= xmem_rom(to_integer(addr));
+		end if;
+	end process;
+
+PROM_WRITE: 
+	process(jtag_ld_clk, jtag_ld_we)
+	begin
+		if rising_edge(jtag_ld_clk) then
+			if jtag_ld_we = '1' then
+				xmem_rom(to_integer(jtag_ld_addr)) <= jtag_ld_din;
+			else	
+				jtag_ld_dout <= xmem_rom(to_integer(jtag_ld_addr));
+			end if;
+		end if;	
+	end process;
+
+--------------------------------------------------------------------------
+end loadable;
diff --git a/lib/CPUs/JCpu/src/tb_cpu_embedded_with_uart.vhd b/lib/CPUs/JCpu/src/tb_cpu_embedded_with_uart.vhd
new file mode 100644
index 0000000..8043410
--- /dev/null
+++ b/lib/CPUs/JCpu/src/tb_cpu_embedded_with_uart.vhd
@@ -0,0 +1,132 @@
+-------------------------------------------------------------------------
+-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
+-- This file: testbench for embedded cpu with rom
+--
+-- Copyright (C) 2007 J. Ahrensfeld
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
+--
+-- For questions and ideas, please contact the author at jens@jayfield.org
+--
+--------------------------------------------------------------------------
+
+LIBRARY ieee;
+use IEEE.STD_LOGIC_1164.ALL;
+USE ieee.numeric_std.ALL;
+use std.textio.all; --  Imports the standard textio package.
+
+library work;
+use work.cpu_pkg.all;
+
+ENTITY tb_cpu_embedded_with_uart IS
+END tb_cpu_embedded_with_uart;
+
+ARCHITECTURE behavior OF tb_cpu_embedded_with_uart IS 
+
+	COMPONENT cpu_embedded_with_uart
+	Port (
+		rst			: in  STD_LOGIC;
+		clk			: in  STD_LOGIC;
+		ce			: in  STD_LOGIC;
+		int_in		: in  STD_LOGIC;
+		int_ack		: out  STD_LOGIC;
+		xmem_we		: out STD_LOGIC;
+		xmem_re		: out STD_LOGIC;
+		xmem_din	: in  unsigned (DMEM_DATA_WIDTH-1 downto 0);
+		xmem_dout	: out unsigned (DMEM_DATA_WIDTH-1 downto 0);
+		xmem_addr	: out unsigned (DMEM_ADDR_WIDTH-1 downto 0);
+		io_sel		: out STD_LOGIC;
+		uart_tx		: out STD_LOGIC;
+		uart_rx		: in  STD_LOGIC
+	);
+	END COMPONENT;
+
+	constant CLK_PERIOD : time := 10 ns;
+	type sram_t is array (integer range <>) of dmem_data_t;
+	signal rst : std_logic := '1';
+	signal clk : std_logic := '1';
+	signal ce  : std_logic := '0';
+	signal int_in : std_logic := '0';
+	signal int_ack : std_logic;
+	signal xmem_din : dmem_data_t := (others => '-');
+	signal xmem_dout : dmem_data_t;
+	signal xmem_addr : dmem_addr_t;
+	signal xmem_we : std_logic;
+	signal xmem_re : std_logic;
+	signal io_sel : std_logic;
+	signal sram : sram_t(0 to 2**dmem_addr_t'length-1);
+	signal uart_tx : std_logic;
+	signal uart_rx : std_logic := '1';
+	
+
+BEGIN
+
+uut: cpu_embedded_with_uart
+	PORT MAP
+	(
+		rst => rst,
+		clk => clk,
+		ce => ce,
+		int_in => int_in,
+		int_ack => int_ack,
+		xmem_we => xmem_we,
+		xmem_re => xmem_re,
+		xmem_din => xmem_din,
+		xmem_dout => xmem_dout,
+		xmem_addr => xmem_addr,
+		io_sel => io_sel,
+		uart_tx => uart_tx,
+		uart_rx => uart_rx
+	);
+
+CLK_GEN: process
+	begin
+		wait for CLK_PERIOD/2;
+		clk <= not clk;
+	end process;
+
+STIMULUS: process
+
+	begin
+
+		wait for 3*CLK_PERIOD;
+		rst <= '0';
+		wait for 2*CLK_PERIOD;
+	
+		wait until rising_edge(clk);
+		ce <= '1';
+	
+		wait for 1000*CLK_PERIOD;
+
+		wait; 
+	
+	end process;
+
+SRAM_RW: process(rst, clk, xmem_addr, xmem_dout, xmem_we)
+	begin
+		if (rst = '1') then
+			xmem_din <= X"00";
+		elsif rising_edge(clk) then
+			if io_sel = '0' then
+				if xmem_we = '1' then	
+					sram(to_integer(xmem_addr)) <= xmem_dout;
+				end if;	
+				xmem_din <= to_01(sram(to_integer(xmem_addr)));
+			else
+				xmem_din <= X"FF";
+			end if;	
+		end if;
+	end process;
+	
+END;