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- compile clean with Intel Quartus Prime Lite 21

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jens
2022-08-07 14:26:12 +02:00
parent 858948adb6
commit cbc093e6e7
1 changed files with 238 additions and 235 deletions
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projects/mips_de0_nano/quartus/mips/JMips.qsf
+22 -19
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@@ -81,12 +81,12 @@ set_global_assignment -name DEVICE EP4CE22F17C6
set_global_assignment -name TOP_LEVEL_ENTITY mips_sys set_global_assignment -name TOP_LEVEL_ENTITY mips_sys
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 14.0 set_global_assignment -name ORIGINAL_QUARTUS_VERSION 14.0
set_global_assignment -name PROJECT_CREATION_TIME_DATE "08:21:44 MAY 14, 2015" set_global_assignment -name PROJECT_CREATION_TIME_DATE "08:21:44 MAY 14, 2015"
set_global_assignment -name LAST_QUARTUS_VERSION 15.0.0 set_global_assignment -name LAST_QUARTUS_VERSION "21.1.1 Lite Edition"
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1 set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)" set_global_assignment -name EDA_SIMULATION_TOOL "Questa Intel FPGA (VHDL)"
set_global_assignment -name EDA_RUN_TOOL_AUTOMATICALLY OFF -section_id eda_simulation set_global_assignment -name EDA_RUN_TOOL_AUTOMATICALLY OFF -section_id eda_simulation
set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
@@ -256,7 +256,7 @@ set_location_assignment PIN_D3 -to uart_rx[0]
set_location_assignment PIN_A3 -to uart_rx[1] set_location_assignment PIN_A3 -to uart_rx[1]
set_location_assignment PIN_C3 -to uart_tx[0] set_location_assignment PIN_C3 -to uart_tx[0]
set_location_assignment PIN_B4 -to uart_tx[1] set_location_assignment PIN_B4 -to uart_tx[1]
set_global_assignment -name VHDL_FILE "Z:/work/repos/mips/src/bootloader/build/denano/eb/bootloader.elf.ROM.vhd" set_global_assignment -name VHDL_FILE bootloader/bootloader.elf.ROM.vhd
set_global_assignment -name VHDL_FILE ../../../../lib/spi/src/spi_flash_wb.vhd set_global_assignment -name VHDL_FILE ../../../../lib/spi/src/spi_flash_wb.vhd
set_global_assignment -name VHDL_FILE ../../../../lib/spi/src/spi_types.vhd set_global_assignment -name VHDL_FILE ../../../../lib/spi/src/spi_types.vhd
set_global_assignment -name VHDL_FILE ../../../../lib/spi/src/spi_master.vhd set_global_assignment -name VHDL_FILE ../../../../lib/spi/src/spi_master.vhd
@@ -270,29 +270,32 @@ set_global_assignment -name VHDL_FILE ../../../../lib/SDRAM/ddr_sdr_v1_5/src/sdr
set_global_assignment -name VHDL_FILE ../../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl.vhd set_global_assignment -name VHDL_FILE ../../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl.vhd
set_global_assignment -name VHDL_FILE ../../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_const.vhd set_global_assignment -name VHDL_FILE ../../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_const.vhd
set_global_assignment -name VHDL_FILE ../../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_cmd.vhd set_global_assignment -name VHDL_FILE ../../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_cmd.vhd
set_global_assignment -name VHDL_FILE ../../../../lib/SDRAM/ddr_sdr_v1_5/src/sdr_phy_de0nano.vhd set_global_assignment -name VHDL_FILE ../../../../lib/SDRAM/ddr_sdr_v1_5/src/phy/altera/sdr_phy_de0nano.vhd
set_global_assignment -name VHDL_FILE ../../../../lib/SDRAM/ddr_sdr_v1_5/src/sdr_clk_cycloneive.vhd set_global_assignment -name VHDL_FILE ../../../../lib/SDRAM/ddr_sdr_v1_5/src/clock/altera/sdr_clk_cycloneive.vhd
set_global_assignment -name VHDL_FILE ../../../../lib/SDRAM/ddr_sdr_v1_5/src/ctrl_sdr_wb32.vhd set_global_assignment -name VHDL_FILE ../../../../lib/SDRAM/ddr_sdr_v1_5/src/ctrl_sdr_wb32.vhd
set_global_assignment -name VHDL_FILE ../../../../lib/uart/uart_types.vhd set_global_assignment -name VHDL_FILE ../../../../lib/uart/src/uart_types.vhd
set_global_assignment -name VHDL_FILE ../../../../lib/misc/bbfifo.vhd set_global_assignment -name VHDL_FILE ../../../../lib/misc/bbfifo/src/bbfifo.vhd
set_global_assignment -name VHDL_FILE ../../../../lib/uart/uart_tx.vhd set_global_assignment -name VHDL_FILE ../../../../lib/uart/src/generic/uart_tx.vhd
set_global_assignment -name VHDL_FILE ../../../../lib/uart/uart_rx.vhd set_global_assignment -name VHDL_FILE ../../../../lib/uart/src/generic/uart_rx.vhd
set_global_assignment -name VHDL_FILE ../../../../lib/uart/uart.vhd set_global_assignment -name VHDL_FILE ../../../../lib/uart/src/generic/uart.vhd
set_global_assignment -name VHDL_FILE ../../../../lib/uart/juart_tx.vhd set_global_assignment -name VHDL_FILE ../../../../lib/uart/src/generic/juart/juart_tx.vhd
set_global_assignment -name VHDL_FILE ../../../../lib/uart/juart_rx.vhd set_global_assignment -name VHDL_FILE ../../../../lib/uart/src/generic/juart/juart_rx.vhd
set_global_assignment -name VHDL_FILE ../../../../lib/uart/uart_wb.vhd set_global_assignment -name VHDL_FILE ../../../../lib/uart/src/uart_wb.vhd
set_global_assignment -name VHDL_FILE ../../../../lib/rams/dpram_1w1r1c_ra_alt.vhd set_global_assignment -name VHDL_FILE ../../../../lib/rams/altera/src/dpram_1w1r1c_ra.vhd
set_global_assignment -name VHDL_FILE ../../../../lib/misc/gpio_wb.vhd set_global_assignment -name VHDL_FILE ../../../../lib/JBUS/gpio/src/gpio_wb.vhd
set_global_assignment -name VHDL_FILE ../../../../lib/misc/utils_pkg.vhd set_global_assignment -name VHDL_FILE ../../../../lib/misc/utils_pkg.vhd
set_global_assignment -name VHDL_FILE ../../../../lib/misc/rom_wb.vhd set_global_assignment -name VHDL_FILE ../../../../lib/JBUS/memory/src/rom_wb.vhd
set_global_assignment -name VHDL_FILE ../../../../lib/misc/ram_wb.vhd set_global_assignment -name VHDL_FILE ../../../../lib/JBUS/memory/src/ram_wb.vhd
set_global_assignment -name VHDL_FILE ../../../../lib/rams/altera/dpram_1w1r2c_ra.vhd set_global_assignment -name VHDL_FILE ../../../../lib/rams/altera/src/dpram_1w1r2c_ra.vhd
set_global_assignment -name VHDL_FILE ../../../../lib/rams/altera/dpram_2w2r2c_ra.vhd set_global_assignment -name VHDL_FILE ../../../../lib/rams/altera/src/dpram_2w2r2c_ra.vhd
set_global_assignment -name VHDL_FILE ../../../../lib/FIFO/src/fifo_sync_ctrl.vhd set_global_assignment -name VHDL_FILE ../../../../lib/FIFO/src/fifo_sync_ctrl.vhd
set_global_assignment -name VHDL_FILE ../../../../lib/FIFO/src/reg_stage.vhd
set_global_assignment -name VHDL_FILE ../../../../lib/FIFO/src/fifo_sync_stage.vhd
set_global_assignment -name VHDL_FILE ../../../../lib/FIFO/src/fifo_sync.vhd set_global_assignment -name VHDL_FILE ../../../../lib/FIFO/src/fifo_sync.vhd
set_global_assignment -name VHDL_FILE ../../../../lib/FIFO/src/fifo_ctrl_pkg.vhd set_global_assignment -name VHDL_FILE ../../../../lib/FIFO/src/fifo_ctrl_pkg.vhd
set_global_assignment -name VHDL_FILE ../../../../lib/FIFO/src/gray_counter.vhd set_global_assignment -name VHDL_FILE ../../../../lib/FIFO/src/gray_counter.vhd
set_global_assignment -name VHDL_FILE ../../../../lib/FIFO/src/fifo_async_ctrl.vhd set_global_assignment -name VHDL_FILE ../../../../lib/FIFO/src/fifo_async_ctrl.vhd
set_global_assignment -name VHDL_FILE ../../../../lib/FIFO/src/fifo_async_stage.vhd
set_global_assignment -name VHDL_FILE ../../../../lib/FIFO/src/fifo_async.vhd set_global_assignment -name VHDL_FILE ../../../../lib/FIFO/src/fifo_async.vhd
set_global_assignment -name VHDL_FILE ../../../../lib/CPUs/MIPS/src/core/mips_types.vhd set_global_assignment -name VHDL_FILE ../../../../lib/CPUs/MIPS/src/core/mips_types.vhd
set_global_assignment -name VHDL_FILE ../../../../lib/CPUs/MIPS/src/core/mips_top.vhd set_global_assignment -name VHDL_FILE ../../../../lib/CPUs/MIPS/src/core/mips_top.vhd