- added and moved

git-svn-id: http://moon:8086/svn/vhdl/trunk@1449 cc03376c-175c-47c8-b038-4cd826a8556b

lib/fixed/ieee/test.vhd

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+--------------------------------------------------------------------------------
+--------------------------------------------------------------------------------
+LIBRARY ieee;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.MATH_REAL.ALL;
+USE ieee.numeric_std.ALL;
+use std.textio.all; --  Imports the standard textio package.
+
+library ieee;
+use ieee.fixed_float_types.all;
+use ieee.fixed_pkg.all;
+
+library work;
+use work.fixed_util_pkg.all;
+
+
+ENTITY test IS
+	Generic (
+	        nbits			: integer := 32;
+	        nbits_frac		: integer := 30;
+	        nbits_out		: integer := 32;
+	        nbits_frac_out	: integer := 31
+	        );
+END test;
+
+ARCHITECTURE behavior OF test IS 
+
+	--Constants
+	constant num_cycles : integer := 5;
+	constant num_steps_per_cycle : integer := 100;
+	constant PERIOD : time := 10 ns;
+
+	constant one_sfix  : sfixed := to_sfixed(1.0, sproto(nbits, nbits_frac));
+	constant zero_sfix : sfixed := to_sfixed(0.0, sproto(nbits, nbits_frac));
+	constant pi1_sfix : sfixed := to_sfixed(3.141592653589793, sproto(nbits, nbits_frac));
+	constant pi2_sfix : sfixed := to_sfixed(3.141592653589793/2.0, sproto(nbits, nbits_frac));
+	
+	--Inputs
+	SIGNAL clk :  std_logic := '0';
+	SIGNAL rst :  std_logic := '1';
+	SIGNAL ce  :  std_logic := '0';
+	SIGNAL xin, yin, zin : sfixed(sproto(nbits, nbits_frac)'range) := zero_sfix;
+	
+		
+BEGIN
+
+ 	tb_clk : PROCESS
+	BEGIN
+		clk <= not clk;
+		wait for PERIOD/2;
+	END PROCESS;
+
+END;