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- fixed spi reset

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git-svn-id: http://moon:8086/svn/vhdl/trunk@1285 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
jens
2015-06-04 15:55:58 +00:00
parent 97543c8bbd
commit c9d75c5d52
1 changed files with 9 additions and 19 deletions
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lib/spi/src/spi_master.vhd
+9 -19
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@@ -49,12 +49,12 @@ ARCHITECTURE behavior OF spi_master IS
signal xfer_count_en : std_logic; signal xfer_count_en : std_logic;
signal xfer_count_busy : std_logic; signal xfer_count_busy : std_logic;
signal data_count_busy : std_logic; signal data_count_busy : std_logic;
signal spi_clk : std_logic := '0'; signal spi_clk : std_logic;
signal spi_clk_out : std_logic; signal spi_clk_out : std_logic;
signal clk_en : std_logic; signal clk_en : std_logic;
signal spi_clk_write : std_logic; signal spi_clk_write : std_logic;
signal spi_clk_read : std_logic; signal spi_clk_read : std_logic;
signal spi_rst_count : unsigned(5 downto 0); signal spi_rst_count : unsigned(3 downto 0);
signal spi_rst : std_logic; signal spi_rst : std_logic;
signal cat_fifo_din : unsigned(SIZEOF_CMD-1 downto 0); signal cat_fifo_din : unsigned(SIZEOF_CMD-1 downto 0);
@@ -174,23 +174,6 @@ begin
); );
-------------------------------------------------------------------------- --------------------------------------------------------------------------
proc_spi_rst_gen:
process(clk)
begin
if rising_edge(clk) then
if rst = '1' then
spi_rst <= '1';
spi_rst_count <= (others => '1');
else
if spi_rst_count /= to_unsigned(0, spi_rst_count'length) then
spi_rst_count <= spi_rst_count - 1;
else
spi_rst <= '0';
end if;
end if ;
end if;
end process;
proc_spi_clk_divider: proc_spi_clk_divider:
process(clk) process(clk)
begin begin
@@ -198,9 +181,16 @@ begin
spi_clk_div_en <= '0'; spi_clk_div_en <= '0';
if rst = '1' then if rst = '1' then
spi_clk_div_count <= (others => '0'); spi_clk_div_count <= (others => '0');
spi_rst_count <= (others => '1');
spi_rst <= '1';
elsif spi_clk_div_count = ctrl.clk_div then elsif spi_clk_div_count = ctrl.clk_div then
spi_clk_div_count <= (others => '0'); spi_clk_div_count <= (others => '0');
spi_clk_div_en <= '1'; spi_clk_div_en <= '1';
if spi_rst_count /= to_unsigned(0, spi_rst_count'length) then
spi_rst_count <= spi_rst_count - 1;
else
spi_rst <= '0';
end if;
else else
spi_clk_div_count <= spi_clk_div_count + 1; spi_clk_div_count <= spi_clk_div_count + 1;
end if; end if;