diff --git a/projects/mips_sys/ise101/mips_sys/mips_sys.prj b/projects/mips_sys/ise101/mips_sys/mips_sys.prj
index 9e78e5f..bf18331 100644
--- a/projects/mips_sys/ise101/mips_sys/mips_sys.prj
+++ b/projects/mips_sys/ise101/mips_sys/mips_sys.prj
@@ -30,15 +30,14 @@ vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_top.vhd"
 vhdl work "../../../../lib/misc/async_types.vhd"
 vhdl work "../../../../lib/FIFO/src/fifo_sync.vhd"
 vhdl work "../../../../lib/ac97_ctrl/src/core/ac_io.vhd"
+vhdl work "../../src/clockgen_virtex4.vhd"
 vhdl work "../../src/async_defs.vhd"
 vhdl work "../../../../lib/VGA_ctrl/src/vga_frontend64.vhd"
-vhdl work "../../../../lib/VGA_ctrl/src/clkgen_virtex4.vhd"
 vhdl work "../../../../lib/uart/uart_wb.vhd"
 vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_frontend64_wb.vhd"
 vhdl work "../../../../lib/misc/rom_wb.vhd"
 vhdl work "../../../../lib/misc/lcd_port.vhd"
 vhdl work "../../../../lib/misc/gpio_wb.vhd"
-vhdl work "../../../../lib/misc/clockgen_virtex4.vhd"
 vhdl work "../../../../lib/misc/async_port_wb.vhd"
 vhdl work "../../../../lib/CPUs/MIPS/src/core/mips_types.vhd"
 vhdl work "../../../../lib/ac97_ctrl/src/core/ac97_wb.vhd"
diff --git a/projects/mips_sys/ise101/mips_sys/mips_sys_vhdl.prj b/projects/mips_sys/ise101/mips_sys/mips_sys_vhdl.prj
index 4b52d29..d225685 100644
--- a/projects/mips_sys/ise101/mips_sys/mips_sys_vhdl.prj
+++ b/projects/mips_sys/ise101/mips_sys/mips_sys_vhdl.prj
@@ -30,15 +30,14 @@ vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_5\src\sdram_ctrl_top.vhd"
 vhdl work "W:\vhdl\lib\misc\async_types.vhd"
 vhdl work "W:\vhdl\lib\FIFO\src\fifo_sync.vhd"
 vhdl work "W:\vhdl\lib\ac97_ctrl\src\core\ac_io.vhd"
+vhdl work "W:\vhdl\projects\mips_sys\src\clockgen_virtex4.vhd"
 vhdl work "W:\vhdl\projects\mips_sys\src\async_defs.vhd"
 vhdl work "W:\vhdl\lib\VGA_ctrl\src\vga_frontend64.vhd"
-vhdl work "W:\vhdl\lib\VGA_ctrl\src\clkgen_virtex4.vhd"
 vhdl work "W:\vhdl\lib\uart\uart_wb.vhd"
 vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_5\src\sdram_ctrl_frontend64_wb.vhd"
 vhdl work "W:\vhdl\lib\misc\rom_wb.vhd"
 vhdl work "W:\vhdl\lib\misc\lcd_port.vhd"
 vhdl work "W:\vhdl\lib\misc\gpio_wb.vhd"
-vhdl work "W:\vhdl\lib\misc\clockgen_virtex4.vhd"
 vhdl work "W:\vhdl\lib\misc\async_port_wb.vhd"
 vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_types.vhd"
 vhdl work "W:\vhdl\lib\ac97_ctrl\src\core\ac97_wb.vhd"