From c9900e509a40923945f9e38d17080b5134f9b213 Mon Sep 17 00:00:00 2001 From: Jens Ahrensfeld Date: Tue, 21 Oct 2008 18:24:56 +0000 Subject: [PATCH] - Loading app from Flash instead User ROM - Removed User ROM git-svn-id: http://moon:8086/svn/vhdl/trunk@91 cc03376c-175c-47c8-b038-4cd826a8556b --- projects/mips_sys/src/mips_sys_sim.vhd | 166 +++++++++++++++---------- projects/mips_sys/src/tb_mips_sys.vhd | 45 +++---- 2 files changed, 117 insertions(+), 94 deletions(-) diff --git a/projects/mips_sys/src/mips_sys_sim.vhd b/projects/mips_sys/src/mips_sys_sim.vhd index 8c79aac..da74301 100644 --- a/projects/mips_sys/src/mips_sys_sim.vhd +++ b/projects/mips_sys/src/mips_sys_sim.vhd @@ -60,12 +60,6 @@ PORT sys_rx : in std_logic; sys_tx : out std_logic; - -- User ROM - sys_user_rom_addr : out word_t; - sys_user_rom_din : in word_t; - sys_user_rom_clk : out std_logic; - sys_user_rom_en : out std_logic; - -- LCD sys_lcd_d : inout unsigned(3 downto 0); sys_lcd_e : out std_logic; @@ -232,6 +226,39 @@ ARCHITECTURE behavior OF mips_sys IS ); END COMPONENT; + COMPONENT flash_port_wb + GENERIC + ( + addr_width : natural := 32; + data_width : natural := 32; + async_timespec : async_timespec_t + ); + PORT + ( + CLK_I : in STD_LOGIC; + RST_I : in STD_LOGIC; + CYC_I : in STD_LOGIC; + STB_I : in STD_LOGIC; + WE_I : in STD_LOGIC; + ACK_O : out STD_LOGIC; + SRDY_O : out STD_LOGIC; + MRDY_I : in STD_LOGIC; + ADDR_I : in unsigned(31 downto 0); + DAT_I : in unsigned(31 downto 0); + DAT_O : out unsigned(31 downto 0); + port_bsyo : out std_logic; + port_bsyi : in std_logic; + port_a : out unsigned(addr_width-1 downto 0); + port_di : in unsigned(data_width-1 downto 0); + port_do : out unsigned(data_width-1 downto 0); + port_d_drv : out STD_LOGIC; + port_wr : out STD_LOGIC; + port_rd : out STD_LOGIC; + flash_cs : out std_logic; + flash_rst : out std_logic + ); + END COMPONENT; + COMPONENT uart_wb PORT ( @@ -338,13 +365,19 @@ ARCHITECTURE behavior OF mips_sys IS signal ADDR_I_usb : unsigned(31 downto 0); signal ADDR_I_flash : unsigned(31 downto 0); signal ADDR_I_ssram : unsigned(31 downto 0); - signal flash_a : unsigned(24 downto 0); - signal ssram_a : unsigned(24 downto 0); signal ssram_clk : std_logic; + signal ssram_a : unsigned(24 downto 0); + signal ssram_do : unsigned(31 downto 0); signal ssram_oe_n : std_logic; signal ssram_we_n : std_logic; + signal ssram_d_drv : std_logic; + signal ssram_bsy : std_logic; + signal flash_a : unsigned(24 downto 0); + signal flash_do : unsigned(31 downto 0); signal flash_oe_n : std_logic; signal flash_we_n : std_logic; + signal flash_d_drv : std_logic; + signal flash_bsy : std_logic; -- Arbiter constant ARB_MAX_MASTER : natural := 2; @@ -418,11 +451,6 @@ ARCHITECTURE behavior OF mips_sys IS signal SRDY_O_gpio : std_logic; signal SDAT_O_gpio : unsigned(31 downto 0); - signal CYC_I_urom : std_logic; - signal ACK_O_urom : std_logic; - signal SRDY_O_urom : std_logic; - signal SDAT_O_urom : unsigned(31 downto 0); - signal CYC_I_uart : std_logic; signal ACK_O_uart : std_logic; signal SRDY_O_uart : std_logic; @@ -447,6 +475,7 @@ ARCHITECTURE behavior OF mips_sys IS -- DDR SDRAM constant BURST_LEN : natural := 2; + constant topad : time := 3 ns; -- attribute rom_style: string; @@ -454,7 +483,7 @@ ARCHITECTURE behavior OF mips_sys IS -- attribute rom_style of cpu_cpu_write_fifo_dout: signal is "DISTRIBUTED"; -- attribute rom_style of cpu_read_fifo_dout: signal is "DISTRIBUTED"; - type mem_area_t is (mem_dead, mem_urom, mem_flash, mem_ssram, mem_usb, mem_rom, mem_ram, mem_gpio, mem_uart, mem_sdram, mem_vga); + type mem_area_t is (mem_dead, mem_flash, mem_ssram, mem_usb, mem_rom, mem_ram, mem_gpio, mem_uart, mem_sdram, mem_vga); signal mem_area : mem_area_t; BEGIN @@ -471,9 +500,31 @@ BEGIN ADDR_I_flash <= "0000000" & ADDR_O(25 downto 2) & '0'; ADDR_I_ssram <= ("0000000000000" & ADDR_O(19 downto 2)) & '0'; - sys_flash_ssram_a <= flash_a when CYC_I_flash = '1' else ssram_a; - sys_flash_ssram_we_n <= ssram_we_n and flash_we_n; - sys_flash_ssram_oe_n <= ssram_oe_n and flash_oe_n; + +sys_flash_ssram_out: + process(clk) + begin + if rising_edge(clk) then + sys_flash_ssram_d <= (others => 'Z') after topad; + sys_flash_ssram_oe_n <= '1'; + sys_flash_ssram_we_n <= '1'; + if flash_bsy = '1' then + sys_flash_ssram_oe_n <= flash_oe_n; + sys_flash_ssram_we_n <= flash_we_n; + sys_flash_ssram_a <= flash_a after topad; + if flash_d_drv = '1' then + sys_flash_ssram_d <= flash_do after topad; + end if; + elsif ssram_bsy = '1' then + sys_flash_ssram_oe_n <= ssram_oe_n; + sys_flash_ssram_we_n <= ssram_we_n; + sys_flash_ssram_a <= ssram_a after topad; + if ssram_d_drv = '1' then + sys_flash_ssram_d <= ssram_do after topad; + end if; + end if; + end if; + end process; --------------------------------------------------------------- -- Arbiter @@ -526,7 +577,7 @@ mem_mux: begin mem_area <= mem_dead; if ADDR_O(31 downto 28) = X"0" then - mem_area <= mem_urom; + mem_area <= mem_flash; elsif ADDR_O(31 downto 28) = X"A" then if ADDR_O(27 downto 26) = "00" then if ADDR_O(17 downto 16) = "00" then @@ -549,7 +600,7 @@ mem_mux: mem_area <= mem_ram; -- mem_area <= mem_ssram; elsif (ADDR_O(31 downto 28) = X"8" or ADDR_O(30) = '1') then - mem_area <= mem_sdram; + mem_area <= mem_ssram; end if; end process; @@ -557,7 +608,6 @@ signal_mux: process(mem_area, CYC_O) begin - CYC_I_urom <= '0'; CYC_I_uart <= '0'; CYC_I_gpio <= '0'; CYC_I_flash <= '0'; @@ -570,9 +620,6 @@ signal_mux: case mem_area is - when mem_urom => - CYC_I_urom <= CYC_O; - when mem_gpio => CYC_I_gpio <= CYC_O; @@ -606,28 +653,13 @@ signal_mux: end process; - sys_user_rom_addr <= ADDR_O; - sys_user_rom_clk <= clk; - sys_user_rom_en <= CYC_I_urom and STB_O; - SDAT_O_urom <= sys_user_rom_din; - SRDY_O_urom <= CYC_I_urom; - -urom_ack_register: - process(clk) - begin - if rising_edge(clk) then - ACK_O_urom <= CYC_I_urom and STB_O; - end if; - end process; - ------------------------------------------------------------------ - SRDY_I <= SRDY_O_flash or SRDY_O_ssram or SRDY_O_usb or SRDY_O_sdram or SRDY_O_ram or SRDY_O_rom or SRDY_O_urom or SRDY_O_uart or SRDY_O_gpio or SRDY_O_vga; - ACK_I <= ACK_O_flash or ACK_O_usb or ACK_O_sdram or ACK_O_ssram or ACK_O_ram or ACK_O_rom or ACK_O_urom or ACK_O_uart or ACK_O_gpio or ACK_O_vga; + SRDY_I <= SRDY_O_flash or SRDY_O_ssram or SRDY_O_usb or SRDY_O_sdram or SRDY_O_ram or SRDY_O_rom or SRDY_O_uart or SRDY_O_gpio or SRDY_O_vga; + ACK_I <= ACK_O_flash or ACK_O_usb or ACK_O_sdram or ACK_O_ssram or ACK_O_ram or ACK_O_rom or ACK_O_uart or ACK_O_gpio or ACK_O_vga; MDAT_I <= SDAT_O_ssram when CYC_I_ssram = '1' else SDAT_O_sdram when CYC_I_sdram = '1' else SDAT_O_ram when CYC_I_ram = '1' else SDAT_O_rom when CYC_I_rom = '1' else - SDAT_O_urom when CYC_I_urom = '1' else SDAT_O_flash when CYC_I_flash = '1' else SDAT_O_usb when CYC_I_usb = '1' else SDAT_O_uart when CYC_I_uart = '1' else @@ -722,8 +754,7 @@ inst_gpio_wb : gpio_wb sys_gpi1 => gpi1 ); - -inst_flash_port : async_port_wb +inst_flash_port : flash_port_wb GENERIC MAP ( addr_width => 25, @@ -743,12 +774,16 @@ inst_flash_port : async_port_wb ADDR_I => ADDR_I_flash, DAT_I => MDAT_O, DAT_O => SDAT_O_flash, - async_a => flash_a, - async_d => sys_flash_ssram_d, - async_cs => sys_flash_ce, - async_wr => flash_we_n, - async_rd => flash_oe_n, - async_rst => sys_flash_rstn + port_bsyo => flash_bsy, + port_bsyi => ssram_bsy, + port_a => flash_a, + port_di => sys_flash_ssram_d, + port_do => flash_do, + port_d_drv => flash_d_drv, + port_wr => flash_we_n, + port_rd => flash_oe_n, + flash_cs => sys_flash_ce, + flash_rst => sys_flash_rstn ); inst_usb_port : async_port_wb @@ -800,8 +835,7 @@ inst_uart_wb : uart_wb ser_tx => sys_tx ); - -inst_ssram_frontend_wb : entity work.ssram_frontend_wb +inst_ssram_port_wb : entity work.ssram_port_wb GENERIC MAP ( addr_width => 25, @@ -827,17 +861,21 @@ inst_ssram_frontend_wb : entity work.ssram_frontend_wb -- Sync SRAM domain ssram_clk_o => sys_ssram_clk, ssram_clk_fb => sys_ssram_clk_fb, - ssram_cke_n => sys_ssram_cke_n, - ssram_ce_n => sys_ssram_ce_n, - ssram_oe_n => ssram_oe_n, - ssram_we_n => ssram_we_n, - ssram_adv => sys_ssram_adv, - ssram_mode => sys_ssram_mode, - ssram_zz => sys_ssram_zz, - ssram_a => ssram_a, - ssram_d => sys_flash_ssram_d, - ssram_dp => sys_ssram_dp, - ssram_bw_n => sys_ssram_bw_n + ssram_cke_n => sys_ssram_cke_n, + ssram_ce_n => sys_ssram_ce_n, + port_bsyo => ssram_bsy, + port_bsyi => flash_bsy, + port_di => sys_flash_ssram_d, + port_do => ssram_do, + port_d_drv => ssram_d_drv, + port_wr => ssram_we_n, + port_rd => ssram_oe_n, + port_a => ssram_a, + ssram_adv => sys_ssram_adv, + ssram_mode => sys_ssram_mode, + ssram_zz => sys_ssram_zz, + ssram_dp => sys_ssram_dp, + ssram_bw_n => sys_ssram_bw_n ); inst_sdram_ctrl_frontend_wb : entity work.sdram_ctrl_frontend_wb @@ -906,9 +944,9 @@ inst_vga_frontend : vga_frontend ( sys_freq => 100E6, fifo_depth => 2048, - fifo_almost_full_thresh => 1920, - fifo_almost_empty_thresh => 128, - tsvga => ts_vga_testbench + fifo_almost_full_thresh => 1860, + fifo_almost_empty_thresh => 256, + tsvga => ts_vga_800_600_72 ) PORT MAP ( diff --git a/projects/mips_sys/src/tb_mips_sys.vhd b/projects/mips_sys/src/tb_mips_sys.vhd index 0db26b1..2b7e3cb 100644 --- a/projects/mips_sys/src/tb_mips_sys.vhd +++ b/projects/mips_sys/src/tb_mips_sys.vhd @@ -69,12 +69,6 @@ ARCHITECTURE behavior OF tb_mips_sys IS signal sys_error : unsigned(1 downto 0); -- indicates DCM Errors signal sys_sdr_clk_fb : std_logic; - constant UROM_ADDR_WIDTH : integer := 18; - signal sys_user_rom_clk : std_logic; - signal sys_user_rom_en : std_logic; - signal sys_user_rom_din : word_t; - signal sys_user_rom_addr : word_t; - signal sys_usb_d : unsigned(15 downto 0) := (others => '0'); signal sys_usb_a : unsigned(1 downto 0); signal sys_usb_csn : std_logic; @@ -104,8 +98,8 @@ ARCHITECTURE behavior OF tb_mips_sys IS signal flash_reg : word_t; - type urom_data_t is array (natural range 0 to 2**(UROM_ADDR_WIDTH-2)-1) of word_t; - signal urom_data : urom_data_t; + type flash_data_t is array (natural range 0 to 2**16-1) of word_t; + signal flash_data : flash_data_t; BEGIN @@ -131,11 +125,6 @@ uut: entity work.mips_sys sys_lcd_rs => sys_lcd_rs, sys_lcd_rw => sys_lcd_rw, - sys_user_rom_addr => sys_user_rom_addr, - sys_user_rom_din => sys_user_rom_din, - sys_user_rom_en => sys_user_rom_en, - sys_user_rom_clk => sys_user_rom_clk, - sys_sdr_clk_p => sys_sdr_clk_p, sys_sdr_clk_n => sys_sdr_clk_n, sys_sdr_cke_q => sys_sdr_cke_q, @@ -236,35 +225,39 @@ i_mt46v16m16_1 : entity work.mt46v16m16 ); sys_sdr_clk_fb <= sys_sdr_clk_p after 2300 ps; - sys_ssram_clk_fb <= sys_ssram_clk after 4 ns; + sys_ssram_clk_fb <= sys_ssram_clk after 0.5 ns; refresh <= true when falling_edge(sys_sdr_ras_qn) and falling_edge(sys_sdr_cas_qn) and sys_sdr_we_qn='1' else false; sys_usb_d <= X"1234" after 20 ns when sys_usb_csn = '0' and sys_usb_rdn = '0' else (others => 'Z') after 5 ns; + CLK_GEN: process begin wait for CLK_PERIOD/2; sys_clk_in <= not sys_clk_in; end process; -UROM_READ: process(sys_rst_n_in, sys_user_rom_clk) +FLASH_READ: process(sys_rst_n_in, sys_flash_ce, sys_flash_ssram_oe_n, sys_flash_ssram_a) type file_t is file of integer; - file load_urom : file_t open read_mode is "test_bui.bin"; + file load_flash : file_t open read_mode is "test_bui.flash.bin"; variable instr : integer; variable index : natural; variable temp : signed(31 downto 0); begin if sys_rst_n_in = '0' then index := 0; - while not endfile(load_urom) loop - read(load_urom, instr); + while not endfile(load_flash) loop + read(load_flash, instr); temp := to_signed(instr, word_t'length); - urom_data(index) <= unsigned(temp); + flash_data(index) <= unsigned(temp); index := index + 1; end loop; - elsif rising_edge(sys_user_rom_clk) and sys_user_rom_en = '1' then - index := to_integer(sys_user_rom_addr(UROM_ADDR_WIDTH+1 downto 2)); - sys_user_rom_din <= urom_data(index); + else + sys_flash_ssram_d <= (others => 'Z') after 10 ns; + if sys_flash_ssram_oe_n = '0' and sys_flash_ce = '1' then + index := to_integer(sys_flash_ssram_a(24 downto 1)); + sys_flash_ssram_d <= flash_data(index) after 10 ns; + end if; end if; end process; @@ -275,14 +268,6 @@ FLASH_WRITE: process(sys_flash_ce, sys_flash_ssram_we_n, sys_flash_ssram_d) end if; end process; -FLASH_READ: process(sys_flash_ce, sys_flash_ssram_oe_n, flash_reg) - begin - sys_flash_ssram_d <= (others => 'Z') after 10 ns; - if sys_flash_ssram_oe_n = '0' and sys_flash_ce = '1' then - sys_flash_ssram_d <= flash_reg after 10 ns; - end if; - end process; - STIMULUS: process begin