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- added byte alignment support for blitter

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- added constant color blitting
Committed on the Free edition of March Hare Software CVSNT Server.
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git-svn-id: http://moon:8086/svn/vhdl/trunk@911 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
jens
2010-05-14 17:18:17 +00:00
parent 197e65fc28
commit c7f8eea244
2 changed files with 724 additions and 108 deletions
Download Patch File Download Diff File Expand all files Collapse all files
lib/VGA_ctrl/src/tb_vga_frontend64.vhd
+444 -21
View File
@@ -86,6 +86,7 @@ inst_vga_frontend64 : entity work.vga_frontend64
fifo_depth => 2048,
fifo_almost_full_thresh => 2048-128,
fifo_almost_empty_thresh => 512,
BLIT_CHUNK_SIZE => 512,
tsvga => tsvga
)
PORT MAP
@@ -353,7 +354,26 @@ STIMULUS: process
for i in 0 to 99 loop
-- BLIT test
while(true) loop
-- set blit request
CYC_O <= '1';
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '1';
WE_O <= '0';
ADDR_O <= X"0000_0000";
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '0';
CYC_O <= '0';
WE_O <= '0';
wait until rising_edge(CLK_O) and ACK_I = '1';
wait until rising_edge(CLK_O);
if read_reg(8) = '0' then
exit;
end if;
end loop;
-- BLIT aligned => aligned test
-- Read status
CYC_O <= '1';
wait until rising_edge(CLK_O) and SRDY_I = '1';
@@ -363,7 +383,7 @@ STIMULUS: process
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '0';
wait until rising_edge(CLK_O) and ACK_I = '1';
-- set src addr first
-- set source start address
CYC_O <= '1';
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '1';
@@ -372,25 +392,16 @@ STIMULUS: process
ADDR_O <= X"0000_0020";
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '0';
-- set src addr last
CYC_O <= '1';
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '1';
WE_O <= '1';
SDAT_O <= X"4100_0000" + to_unsigned(4*(80*4-1), 32);
ADDR_O <= X"0000_0024";
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '0';
-- set src dim-x
CYC_O <= '1';
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '1';
WE_O <= '1';
SDAT_O <= to_unsigned(4*80, 32);
SDAT_O <= to_unsigned(4*tsvga.ts_h.ncyc_scan, 32);
ADDR_O <= X"0000_0028";
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '0';
-- set dst addr first
-- set destination start address
CYC_O <= '1';
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '1';
@@ -399,12 +410,12 @@ STIMULUS: process
ADDR_O <= X"0000_0050";
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '0';
-- set dst addr last
-- set constant color
CYC_O <= '1';
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '1';
WE_O <= '1';
SDAT_O <= X"4200_0000" + to_unsigned(4*(80*4-1), 32);
SDAT_O <= X"0123_4567";
ADDR_O <= X"0000_0054";
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '0';
@@ -413,7 +424,7 @@ STIMULUS: process
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '1';
WE_O <= '1';
SDAT_O <= to_unsigned(4*80, 32);
SDAT_O <= to_unsigned(4*tsvga.ts_h.ncyc_scan, 32);
ADDR_O <= X"0000_0058";
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '0';
@@ -422,7 +433,7 @@ STIMULUS: process
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '1';
WE_O <= '1';
SDAT_O <= to_unsigned(80-1, 32);
SDAT_O <= to_unsigned(256-1, 32);
ADDR_O <= X"0000_0060";
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '0';
@@ -431,7 +442,7 @@ STIMULUS: process
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '1';
WE_O <= '1';
SDAT_O <= X"0000_0003";
SDAT_O <= to_unsigned(256-1, 32);
ADDR_O <= X"0000_0064";
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '0';
@@ -440,16 +451,428 @@ STIMULUS: process
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '1';
WE_O <= '1';
SDAT_O <= read_reg or X"0000_0100";
SDAT_O <= (read_reg and not X"0001_0000") or X"0000_0100";
ADDR_O <= X"0000_0000";
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '0';
CYC_O <= '0';
WE_O <= '0';
wait for 100000*CLK_PERIOD;
while(true) loop
-- read blit request
CYC_O <= '1';
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '1';
WE_O <= '0';
ADDR_O <= X"0000_0000";
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '0';
CYC_O <= '0';
WE_O <= '0';
wait until rising_edge(CLK_O) and ACK_I = '1';
wait until rising_edge(CLK_O);
if read_reg(8) = '0' then
exit;
end if;
end loop;
-- BLIT unaligned => aligned test
-- Read status
CYC_O <= '1';
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '1';
WE_O <= '0';
ADDR_O <= X"0000_0000";
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '0';
wait until rising_edge(CLK_O) and ACK_I = '1';
-- set source start address
CYC_O <= '1';
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '1';
WE_O <= '1';
SDAT_O <= X"4100_0004";
ADDR_O <= X"0000_0020";
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '0';
-- set src dim-x
CYC_O <= '1';
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '1';
WE_O <= '1';
SDAT_O <= to_unsigned(4*tsvga.ts_h.ncyc_scan, 32);
ADDR_O <= X"0000_0028";
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '0';
-- set destination start address
CYC_O <= '1';
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '1';
WE_O <= '1';
SDAT_O <= X"4200_0000";
ADDR_O <= X"0000_0050";
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '0';
-- set constant color
CYC_O <= '1';
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '1';
WE_O <= '1';
SDAT_O <= X"0123_4567";
ADDR_O <= X"0000_0054";
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '0';
-- set dst dim-x
CYC_O <= '1';
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '1';
WE_O <= '1';
SDAT_O <= to_unsigned(4*tsvga.ts_h.ncyc_scan, 32);
ADDR_O <= X"0000_0058";
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '0';
-- set nx
CYC_O <= '1';
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '1';
WE_O <= '1';
SDAT_O <= to_unsigned(256-1, 32);
ADDR_O <= X"0000_0060";
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '0';
-- set ny
CYC_O <= '1';
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '1';
WE_O <= '1';
SDAT_O <= to_unsigned(256-1, 32);
ADDR_O <= X"0000_0064";
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '0';
-- set blit request
CYC_O <= '1';
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '1';
WE_O <= '1';
SDAT_O <= (read_reg and not X"0001_0000") or X"0000_0100";
ADDR_O <= X"0000_0000";
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '0';
CYC_O <= '0';
WE_O <= '0';
while(true) loop
-- read blit request
CYC_O <= '1';
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '1';
WE_O <= '0';
ADDR_O <= X"0000_0000";
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '0';
CYC_O <= '0';
WE_O <= '0';
wait until rising_edge(CLK_O) and ACK_I = '1';
wait until rising_edge(CLK_O);
if read_reg(8) = '0' then
exit;
end if;
end loop;
-- BLIT aligned => unaligned test
-- Read status
CYC_O <= '1';
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '1';
WE_O <= '0';
ADDR_O <= X"0000_0000";
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '0';
wait until rising_edge(CLK_O) and ACK_I = '1';
-- set source start address
CYC_O <= '1';
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '1';
WE_O <= '1';
SDAT_O <= X"4100_0000";
ADDR_O <= X"0000_0020";
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '0';
-- set src dim-x
CYC_O <= '1';
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '1';
WE_O <= '1';
SDAT_O <= to_unsigned(4*tsvga.ts_h.ncyc_scan, 32);
ADDR_O <= X"0000_0028";
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '0';
-- set destination start address
CYC_O <= '1';
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '1';
WE_O <= '1';
SDAT_O <= X"4200_0004";
ADDR_O <= X"0000_0050";
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '0';
-- set constant color
CYC_O <= '1';
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '1';
WE_O <= '1';
SDAT_O <= X"0123_4567";
ADDR_O <= X"0000_0054";
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '0';
-- set dst dim-x
CYC_O <= '1';
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '1';
WE_O <= '1';
SDAT_O <= to_unsigned(4*tsvga.ts_h.ncyc_scan, 32);
ADDR_O <= X"0000_0058";
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '0';
-- set nx
CYC_O <= '1';
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '1';
WE_O <= '1';
SDAT_O <= to_unsigned(256-1, 32);
ADDR_O <= X"0000_0060";
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '0';
-- set ny
CYC_O <= '1';
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '1';
WE_O <= '1';
SDAT_O <= to_unsigned(256-1, 32);
ADDR_O <= X"0000_0064";
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '0';
-- set blit request
CYC_O <= '1';
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '1';
WE_O <= '1';
SDAT_O <= (read_reg and not X"0001_0000") or X"0000_0100";
ADDR_O <= X"0000_0000";
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '0';
CYC_O <= '0';
WE_O <= '0';
while(true) loop
-- read blit request
CYC_O <= '1';
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '1';
WE_O <= '0';
ADDR_O <= X"0000_0000";
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '0';
CYC_O <= '0';
WE_O <= '0';
wait until rising_edge(CLK_O) and ACK_I = '1';
wait until rising_edge(CLK_O);
if read_reg(8) = '0' then
exit;
end if;
end loop;
-- BLIT const => aligned test
-- Read status
CYC_O <= '1';
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '1';
WE_O <= '0';
ADDR_O <= X"0000_0000";
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '0';
wait until rising_edge(CLK_O) and ACK_I = '1';
-- set source start address
CYC_O <= '1';
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '1';
WE_O <= '1';
SDAT_O <= X"4100_0000";
ADDR_O <= X"0000_0020";
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '0';
-- set src dim-x
CYC_O <= '1';
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '1';
WE_O <= '1';
SDAT_O <= to_unsigned(4*tsvga.ts_h.ncyc_scan, 32);
ADDR_O <= X"0000_0028";
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '0';
-- set destination start address
CYC_O <= '1';
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '1';
WE_O <= '1';
SDAT_O <= X"4200_0000";
ADDR_O <= X"0000_0050";
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '0';
-- set constant color
CYC_O <= '1';
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '1';
WE_O <= '1';
SDAT_O <= X"0123_4567";
ADDR_O <= X"0000_0054";
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '0';
-- set dst dim-x
CYC_O <= '1';
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '1';
WE_O <= '1';
SDAT_O <= to_unsigned(4*tsvga.ts_h.ncyc_scan, 32);
ADDR_O <= X"0000_0058";
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '0';
-- set nx
CYC_O <= '1';
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '1';
WE_O <= '1';
SDAT_O <= to_unsigned(256-1, 32);
ADDR_O <= X"0000_0060";
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '0';
-- set ny
CYC_O <= '1';
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '1';
WE_O <= '1';
SDAT_O <= to_unsigned(256-1, 32);
ADDR_O <= X"0000_0064";
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '0';
-- set blit request
CYC_O <= '1';
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '1';
WE_O <= '1';
SDAT_O <= read_reg or X"0001_0100";
ADDR_O <= X"0000_0000";
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '0';
CYC_O <= '0';
WE_O <= '0';
while(true) loop
-- read blit request
CYC_O <= '1';
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '1';
WE_O <= '0';
ADDR_O <= X"0000_0000";
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '0';
CYC_O <= '0';
WE_O <= '0';
wait until rising_edge(CLK_O) and ACK_I = '1';
wait until rising_edge(CLK_O);
if read_reg(8) = '0' then
exit;
end if;
end loop;
-- BLIT const => unaligned test
-- Read status
CYC_O <= '1';
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '1';
WE_O <= '0';
ADDR_O <= X"0000_0000";
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '0';
wait until rising_edge(CLK_O) and ACK_I = '1';
-- set source start address
CYC_O <= '1';
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '1';
WE_O <= '1';
SDAT_O <= X"4100_0000";
ADDR_O <= X"0000_0020";
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '0';
-- set src dim-x
CYC_O <= '1';
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '1';
WE_O <= '1';
SDAT_O <= to_unsigned(4*tsvga.ts_h.ncyc_scan, 32);
ADDR_O <= X"0000_0028";
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '0';
-- set destination start address
CYC_O <= '1';
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '1';
WE_O <= '1';
SDAT_O <= X"4200_0004";
ADDR_O <= X"0000_0050";
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '0';
-- set constant color
CYC_O <= '1';
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '1';
WE_O <= '1';
SDAT_O <= X"0123_4567";
ADDR_O <= X"0000_0054";
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '0';
-- set dst dim-x
CYC_O <= '1';
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '1';
WE_O <= '1';
SDAT_O <= to_unsigned(4*tsvga.ts_h.ncyc_scan, 32);
ADDR_O <= X"0000_0058";
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '0';
-- set nx
CYC_O <= '1';
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '1';
WE_O <= '1';
SDAT_O <= to_unsigned(256-1, 32);
ADDR_O <= X"0000_0060";
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '0';
-- set ny
CYC_O <= '1';
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '1';
WE_O <= '1';
SDAT_O <= to_unsigned(256-1, 32);
ADDR_O <= X"0000_0064";
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '0';
-- set blit request
CYC_O <= '1';
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '1';
WE_O <= '1';
SDAT_O <= read_reg or X"0001_0100";
ADDR_O <= X"0000_0000";
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '0';
CYC_O <= '0';
WE_O <= '0';
wait for 60000*CLK_PERIOD;
end loop;
wait;