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[spi_flash_wb.vhd]

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- added caching

git-svn-id: http://moon:8086/svn/vhdl/trunk@1296 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
jens
2015-06-13 09:57:36 +00:00
parent f96a017bc7
commit c7eed7504d
2 changed files with 217 additions and 32 deletions
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lib/spi/src/tb_spi_flash_wb.vhd
+51
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@@ -88,6 +88,13 @@ uut : entity work.spi_flash_wb
);
inst_spi_slave: entity work.S25fl064k
GENERIC MAP
(
UserPreload => TRUE,
mem_file_name => "tb_spi_flash_wb.mem",
screg_file_name => "none"
)
PORT MAP (
SCK => mst_clk, -- serial clock input
SI => mosi, -- serial data input
@@ -122,6 +129,50 @@ STIMULUS: process
wait until rising_edge(CLK) and ACK_O = '1';
CYC_I <= '0';
wait for 10*CLK_PERIOD;
wait until rising_edge(CLK);
ADDR_I <= X"0000_0000";
STB_I <= '1';
CYC_I <= '1';
wait until rising_edge(CLK) and SRDY_O = '1';
STB_I <= '0';
wait until rising_edge(CLK) and ACK_O = '1';
CYC_I <= '0';
wait for 10*CLK_PERIOD;
wait until rising_edge(CLK);
ADDR_I <= X"0000_0004";
STB_I <= '1';
CYC_I <= '1';
wait until rising_edge(CLK) and SRDY_O = '1';
STB_I <= '0';
wait until rising_edge(CLK) and ACK_O = '1';
CYC_I <= '0';
wait for 10*CLK_PERIOD;
wait until rising_edge(CLK);
ADDR_I <= X"0000_0100";
STB_I <= '1';
CYC_I <= '1';
wait until rising_edge(CLK) and SRDY_O = '1';
STB_I <= '0';
wait until rising_edge(CLK) and ACK_O = '1';
CYC_I <= '0';
wait for 10*CLK_PERIOD;
CYC_I <= '1';
for i in 0 to 63 loop
ADDR_I <= to_unsigned(4*i, 32);
STB_I <= '1';
wait until rising_edge(CLK) and SRDY_O = '1';
STB_I <= '0';
wait until rising_edge(CLK) and ACK_O = '1';
end loop;
wait for 10*CLK_PERIOD;
CYC_I <= '1';
wait;
end process;