diff --git a/lib/CPUs/MIPS/src/core/mips_pipeline.vhd b/lib/CPUs/MIPS/src/core/mips_pipeline.vhd
index fbdc1e8..06b58da 100644
--- a/lib/CPUs/MIPS/src/core/mips_pipeline.vhd
+++ b/lib/CPUs/MIPS/src/core/mips_pipeline.vhd
@@ -667,7 +667,7 @@ proc_wptr_mux:
 proc_stage_bcu_op:
 	process(clk_1)
 	begin
-		if rising_edge(clk_1) then
+		if rising_edge(clk_1) and sdu.EX_stall = '0' then
 			bcu_op_a		<= ID_stage.reg_a;
 			bcu_op_b		<= ID_stage.reg_b;
 		end if;