diff --git a/lib/CPUs/MIPS/src/core/dcache.vhd b/lib/CPUs/MIPS/src/core/dcache.vhd
index 1e3e5a3..55d6c76 100644
--- a/lib/CPUs/MIPS/src/core/dcache.vhd
+++ b/lib/CPUs/MIPS/src/core/dcache.vhd
@@ -40,6 +40,7 @@ ENTITY dcache IS
 		CLK_I		: in  STD_LOGIC;
 		ACK_I		: in  STD_LOGIC;
 		SRDY_I		: in  STD_LOGIC;
+		MRDY_O		: out STD_LOGIC;
 		ADDR_O		: out word_t;
 		DAT_I		: in  word_t;
 		STB_O		: out STD_LOGIC;
@@ -349,6 +350,7 @@ cache_state_next:
 		end if;
 	end process;	
 
+	MRDY_O				<= fill_count_en;
 	ADDR_O				<= request_addr;
 	
 	cpu_busy			<= cache_busy;
diff --git a/lib/CPUs/MIPS/src/core/icache.vhd b/lib/CPUs/MIPS/src/core/icache.vhd
index e6028a9..0c3b9aa 100644
--- a/lib/CPUs/MIPS/src/core/icache.vhd
+++ b/lib/CPUs/MIPS/src/core/icache.vhd
@@ -40,6 +40,7 @@ ENTITY icache IS
 		CLK_I		: in  STD_LOGIC;
 		ACK_I		: in  STD_LOGIC;
 		SRDY_I		: in  STD_LOGIC;
+		MRDY_O		: out STD_LOGIC;
 		ADDR_O		: out word_t;
 		DAT_I		: in  word_t;
 		STB_O		: out STD_LOGIC;
@@ -313,7 +314,9 @@ cache_state_next:
 		end if;
 	end process;	
 
+	MRDY_O			<= fill_count_en;
 	ADDR_O				<= fill_tag & fill_cache_index & req_word_index & "00";
+	
 	cpu_busy			<= cache_busy;
 	cpu_dout			<= data_ram_data_rd;
 	
diff --git a/lib/CPUs/MIPS/src/core/mips_bui.vhd b/lib/CPUs/MIPS/src/core/mips_bui.vhd
index 3835113..e2aae9f 100644
--- a/lib/CPUs/MIPS/src/core/mips_bui.vhd
+++ b/lib/CPUs/MIPS/src/core/mips_bui.vhd
@@ -82,6 +82,7 @@ architecture behavior of biu is
 		CLK_I		: in  STD_LOGIC;
 		ACK_I		: in  STD_LOGIC;
 		SRDY_I		: in  STD_LOGIC;
+		MRDY_O		: out STD_LOGIC;
 		ADDR_O		: out word_t;
 		DAT_I		: in  word_t;
 		STB_O		: out STD_LOGIC;
@@ -106,6 +107,7 @@ architecture behavior of biu is
 		CLK_I		: in  STD_LOGIC;
 		ACK_I		: in  STD_LOGIC;
 		SRDY_I		: in  STD_LOGIC;
+		MRDY_O		: out STD_LOGIC;
 		ADDR_O		: out word_t;
 		DAT_I		: in  word_t;
 		STB_O		: out STD_LOGIC;
@@ -140,6 +142,8 @@ architecture behavior of biu is
 	signal CYC_O_dmem_wr	: std_logic;
 	signal SRDY_I_icache	: std_logic;
 	signal SRDY_I_dcache	: std_logic;
+	signal MRDY_O_icache	: std_logic;
+	signal MRDY_O_dcache	: std_logic;
 	signal ADDR_O_icache	: word_t;
 	signal ADDR_O_dcache	: word_t;
 	signal ADDR_O_dmem_rd	: word_t;
@@ -244,6 +248,7 @@ inst_icache : icache
 		STB_O		=> STB_O_icache,
 		CYC_O		=> CYC_O_icache,
 		ADDR_O		=> ADDR_O_icache,
+		MRDY_O		=> MRDY_O_icache,
 		DAT_I		=> DAT,
 		ACK_I		=> ACK,
 		SRDY_I		=> SRDY_I_icache,
@@ -269,6 +274,7 @@ inst_dcache : dcache
 		CYC_O		=> CYC_O_dcache,
 		STB_O		=> STB_O_dcache,
 		ADDR_O		=> ADDR_O_dcache,
+		MRDY_O		=> MRDY_O_dcache,
 		DAT_I		=> DAT,
 		ACK_I		=> ACK,
 		SRDY_I		=> SRDY_I_dcache,
@@ -315,7 +321,7 @@ inst_bin_fifo: entity work.fifo_async
 	DAT				<= bin_fifo_dout;
 	ACK				<= not bin_fifo_empty;
 	bin_fifo_we		<= ACK_I;
-	bin_fifo_re		<= read_cycle;
+	bin_fifo_re		<= dmem_mem_rd_gnt or MRDY_O_icache or MRDY_O_dcache;
 	
 -- Instantiate synchronous FIFO
 inst_bout_fifo: entity work.fifo_async