diff --git a/lib/SDRAM/ddr_sdr_v1_5/src/sdr_phy_de0nano.vhd b/lib/SDRAM/ddr_sdr_v1_5/src/sdr_phy_de0nano.vhd
index 05d2b41..c665090 100644
--- a/lib/SDRAM/ddr_sdr_v1_5/src/sdr_phy_de0nano.vhd
+++ b/lib/SDRAM/ddr_sdr_v1_5/src/sdr_phy_de0nano.vhd
@@ -61,9 +61,11 @@ end sdram_phy;
 
 architecture tech of sdram_phy is
 
-	signal data_reg_r		: unsigned(BUS_DATA_WIDTH-1 downto 0);
+	signal data_reg_r		: unsigned(PART_DATA_WIDTH-1 downto 0);
+	signal data_reg_w		: unsigned(PART_DATA_WIDTH-1 downto 0);
+	signal dm_reg_w			: unsigned(PART_DM_WIDTH-1 downto 0);
 	signal part_ctrl_reg	: part_ctrl_t;
-	signal we_reg			: std_logic;
+	signal we_reg			: std_logic;
 	
 	signal clk0				: std_logic;
 	signal clk0_temp		: std_logic;
@@ -86,8 +88,9 @@ architecture tech of sdram_phy is
 
 begin
 
-	clk0_out	<= clk0_temp;
-	clk0		<= clk0_temp after 10 ps;		-- fix delta delay
+--	clk0_out	<= clk0_temp;
+	clk0_out	<= clk0_temp after 10 ps;		-- fix delta delay
+	clk0		<= clk0_temp; -- after 10 ps;		-- fix delta delay
 	rst0_out	<= rst0;
 --	clk0_rd		<= clk_fb;			-- no feedback pin on DE0-Nano, use shifted clk1_0_out from clock gen
 
@@ -169,8 +172,8 @@ part_clk		<= clk0 after TPD_BOARD_SIM;
 	begin  
 		if falling_edge(clk0) then
 			part_data <= (others => 'Z') after TPD_BOARD_SIM;
-			if (phy_ctrl.we = '1') then
-				part_data	<= phy_in.wr_data after TPD_BOARD_SIM;
+			if we_reg = '1' then
+				part_data	<= data_reg_w after TPD_BOARD_SIM;
 			end if;
 		end if;
 	end process;
@@ -180,7 +183,7 @@ part_clk		<= clk0 after TPD_BOARD_SIM;
 	process (clk0) is
 	begin  
 		if falling_edge(clk0) then
-			part_dqm	<= phy_in.wr_dm after TPD_BOARD_SIM;
+			part_dqm	<= dm_reg_w after TPD_BOARD_SIM;
 		end if;
 	end process;
 
@@ -195,11 +198,15 @@ part_clk		<= clk0 after TPD_BOARD_SIM;
 				part_ctrl_reg.cke		<= '0';
 			else
 				part_ctrl_reg 		<= phy_ctrl.part;
-				phy_out.wr_data_re	<= phy_ctrl.we;
+				data_reg_w			<= phy_in.wr_data;
+				dm_reg_w			<= phy_in.wr_dm;
+				we_reg				<= phy_ctrl.we;
 			end if;
 		end if;
 	end process;
 
+	phy_out.wr_data_re	<= phy_ctrl.we;
+	
 	process (clk0) is
 	begin  
 		if falling_edge(clk0) then