diff --git a/lib/CPUs/MIPS/src/core/mips_cop.vhd b/lib/CPUs/MIPS/src/core/mips_cop.vhd index f602db7..e25970d 100644 --- a/lib/CPUs/MIPS/src/core/mips_cop.vhd +++ b/lib/CPUs/MIPS/src/core/mips_cop.vhd @@ -42,6 +42,7 @@ entity cop is clk : in STD_LOGIC; eb : in STD_LOGIC; int : in unsigned(5 downto 0); + nmi : in STD_LOGIC; ir_en : in STD_LOGIC; ir : in word_t; ctrl_in : in cop0_ctrl_in_t; @@ -80,6 +81,7 @@ architecture Behavioral of cop is signal reg_rptr : reg_ptr_t; signal reg_wptr : reg_ptr_t; signal inject_exc : STD_LOGIC; + signal latch_vect_en : STD_LOGIC; type cop_pipe_t is record opc : opcode_t; @@ -158,6 +160,7 @@ exception_state: status_rest <= '0'; inject_exc <= '0'; imem_addr_we <= '0'; + latch_vect_en <= '0'; exc_staten <= exc_state; @@ -181,6 +184,7 @@ exception_state: end if; when exc_commit => + latch_vect_en <= '1'; ctrl_out.exc_pending <= '1'; ctrl_out.exc_commit <= '1'; if ctrl_in.sdu.ID_stall = '0' then @@ -330,7 +334,8 @@ cop_cache_op: cop_ip_reg_write: process(clk) - variable ip_v : unsigned(7 downto 0); + variable ip_v : unsigned(7 downto 0); + variable ipm_v : unsigned(7 downto 0); begin if rising_edge(clk) then if rst = '1' then @@ -340,9 +345,11 @@ cop_ip_reg_write: sw_int <= din(9 downto 8); end if; end if; - ip_v := (int & sw_int) and im; + ip_v := (int & sw_int); + ipm_v := ip_v and im; ip <= ip_v; - ctrl_out.int <= eval_int(ip_v) and status(0); + ctrl_out.int <= (eval_int(ipm_v) and status(0)); + ctrl_out.NMI <= nmi; end if; end process; @@ -352,10 +359,14 @@ cop_exc_vector: if rising_edge(clk) then if rst = '1' then ctrl_out.exc_vec <= X"BFC00000"; - else - ctrl_out.exc_vec <= X"80000080"; - if status(22) = '1' then - ctrl_out.exc_vec <= X"BFC00180"; + elsif latch_vect_en = '1' then + if ctrl_in.events.nmi = '1' then + ctrl_out.exc_vec <= X"BFC00000"; + else + ctrl_out.exc_vec <= X"80000080"; + if status(22) = '1' then + ctrl_out.exc_vec <= X"BFC00180"; + end if; end if; end if; end if;