diff --git a/lib/CPUs/MIPS/src/core/icache.vhd b/lib/CPUs/MIPS/src/core/icache.vhd
index 78733f4..534ff3a 100644
--- a/lib/CPUs/MIPS/src/core/icache.vhd
+++ b/lib/CPUs/MIPS/src/core/icache.vhd
@@ -124,6 +124,7 @@ END COMPONENT;
 	signal  tag_ram_data_rd		: tag_ram_data_t;
 	signal  tag_ram_addr_wr		: unsigned(cache_index_width-1 downto 0);
 	signal  tag_ram_data_wr		: tag_ram_data_t;
+	signal	tag_ram_re			: std_logic;
 	signal	tag_ram_we			: std_logic;
 	
 	signal	ram_index_count			: natural range 0 to 2**word_index_width-1;
@@ -164,7 +165,7 @@ inst_tag_ram : dpram_1w1r
 		clka	=> CLK_I,
 		clkb	=> CLK_I,
 		en_a	=> '1',
-		en_b	=> '1',
+		en_b	=> tag_ram_re,
 		we_a	=> tag_ram_we,
 		addr_a	=> tag_ram_addr_wr,
 		addr_b	=> tag_ram_addr_rd,
@@ -229,6 +230,7 @@ cache_state:
 		CYC_O					<= '0';
 		STB_O					<= '0';
 		data_ram_re				<= '0';
+		tag_ram_re				<= '0';
 		was_miss				<= '0';
 		data_write				<= '0';
 		tag_ram_addr_wr			<= to_unsigned(cache_index_count, cache_index_width);
@@ -251,6 +253,7 @@ cache_state:
 				elsif cpu_en = '1' then
 					cpu_reg_en			<= '1';
 					data_ram_re			<= '1';
+					tag_ram_re			<= '1';
 				end if;	
 			end if;	
 		when flush =>
@@ -264,6 +267,7 @@ cache_state:
 				if cpu_en = '1' then
 					cpu_reg_en			<= '1';
 					data_ram_re			<= '1';
+					tag_ram_re			<= '1';
 				end if;
 			end if;
 		when mem_request =>
@@ -298,6 +302,7 @@ cache_state:
 			sn						<= rd_cache;
 			
 		when rd_cache =>
+			tag_ram_re				<= '1';
 			data_ram_re				<= '1';
 			was_miss				<= '1';
 			sn	<= ready;