diff --git a/lib/CPUs/MIPS/src/core/mips_top.vhd b/lib/CPUs/MIPS/src/core/mips_top.vhd
index 9e4bcdb..d778164 100644
--- a/lib/CPUs/MIPS/src/core/mips_top.vhd
+++ b/lib/CPUs/MIPS/src/core/mips_top.vhd
@@ -29,6 +29,11 @@ library work;
 use work.mips_types.all;
 
 entity mips_top is
+	Generic
+	(
+		icache_size	: natural := 4096;	-- words
+		dcache_size	: natural := 4096	-- words
+	);
 	Port
 	(
 		debug		: out unsigned(1 downto 0);
@@ -36,9 +41,9 @@ entity mips_top is
 		CLK_I		: in  STD_LOGIC;
 		ACK_I		: in  STD_LOGIC;
 		SRDY_I		: in  STD_LOGIC;
-		ADDR_O		: out word_t;
-		DAT_I		: in  word_t;
-		DAT_O		: out word_t;
+		ADDR_O		: out unsigned(31 downto 0);
+		DAT_I		: in  unsigned(31 downto 0);
+		DAT_O		: out unsigned(31 downto 0);
 		WE_O		: out STD_LOGIC;
 		SEL_O		: out unsigned(3 downto 0);
 		CYC_O		: out STD_LOGIC;
@@ -87,7 +92,6 @@ architecture rtl of mips_top is
 	signal dmem_din			: word_t;
 	signal dmem_be			: unsigned(3 downto 0);
 
-
 	COMPONENT biu
 	GENERIC
 	(
@@ -100,9 +104,9 @@ architecture rtl of mips_top is
 		CLK_I			: in  STD_LOGIC;
 		ACK_I			: in  STD_LOGIC;
 		SRDY_I			: in  STD_LOGIC;
-		ADDR_O			: out word_t;
-		DAT_I			: in  word_t;
-		DAT_O			: out word_t;
+		ADDR_O			: out unsigned(31 downto 0);
+		DAT_I			: in  unsigned(31 downto 0);
+		DAT_O			: out unsigned(31 downto 0);
 		WE_O			: out STD_LOGIC;
 		SEL_O			: out unsigned(3 downto 0);
 		CYC_O			: out STD_LOGIC;
@@ -155,8 +159,8 @@ inst_pipeline: pipeline
 inst_biu: biu
 	GENERIC MAP
 	(
-		icache_size	=> 4096,	-- words
-		dcache_size	=> 4096		-- words
+		icache_size	=> icache_size,	-- words
+		dcache_size	=> dcache_size	-- words
 	)
 	PORT MAP
 	(