From c211089a9422a39d87d3b292a6f34a5701e1f4cb Mon Sep 17 00:00:00 2001
From: Jens Ahrensfeld <jens@jayfield.org>
Date: Sat, 3 Apr 2021 13:13:48 +0000
Subject: [PATCH] - added

git-svn-id: http://moon:8086/svn/vhdl/trunk@1627 cc03376c-175c-47c8-b038-4cd826a8556b
---
 lib/uart/ghdl/tb_uart_sim.gtkw | 27 +++++++++++++++++++++++++++
 lib/uart/ghdl/tb_uart_sim.make | 20 ++++++++++++++++++++
 lib/uart/ghdl/uart_sim.inc     | 13 +++++++++++++
 3 files changed, 60 insertions(+)
 create mode 100644 lib/uart/ghdl/tb_uart_sim.gtkw
 create mode 100644 lib/uart/ghdl/tb_uart_sim.make
 create mode 100644 lib/uart/ghdl/uart_sim.inc

diff --git a/lib/uart/ghdl/tb_uart_sim.gtkw b/lib/uart/ghdl/tb_uart_sim.gtkw
new file mode 100644
index 0000000..35339af
--- /dev/null
+++ b/lib/uart/ghdl/tb_uart_sim.gtkw
@@ -0,0 +1,27 @@
+[*]
+[*] GTKWave Analyzer v3.3.104 (w)1999-2020 BSI
+[*] Sat Apr  3 13:13:23 2021
+[*]
+[dumpfile] "/home/jens/work/vhdl/trunk/lib/uart/ghdl/build/tb_uart_sim/tb_uart_sim.fst"
+[dumpfile_mtime] "Sat Apr  3 13:11:53 2021"
+[dumpfile_size] 984
+[savefile] "/home/jens/work/vhdl/trunk/lib/uart/ghdl/build/tb_uart_sim/tb_uart_sim.gtkw"
+[timestart] 0
+[size] 1581 824
+[pos] -1 -1
+*-32.127811 11470000000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
+[sst_width] 233
+[signals_width] 204
+[sst_expanded] 1
+[sst_vpaned_height] 222
+@28
+clk
+@22
+data_rx[7:0]
+data_tx[7:0]
+@28
+tx_ser
+@29
+tx_we
+[pattern_trace] 1
+[pattern_trace] 0
diff --git a/lib/uart/ghdl/tb_uart_sim.make b/lib/uart/ghdl/tb_uart_sim.make
new file mode 100644
index 0000000..a5b4bf4
--- /dev/null
+++ b/lib/uart/ghdl/tb_uart_sim.make
@@ -0,0 +1,20 @@
+# -----------------------------------------------------------
+include $(VHDL_HOME)/make/defs.mk
+# -----------------------------------------------------------
+include $(VHDL_HOME)/lib/uart/ghdl/uart_sim.inc
+
+# -----------------------------------------------------------
+MOD_PATH := $(LIB_PATH)/uart/src
+
+SRCS := $(UART_SIM_SRCS)
+SRCS += $(MOD_PATH)/tb_uart.vhd
+
+# -----------------------------------------------------------
+# Compile
+TARGET := tb_uart_sim
+ENTITY := tb_uart
+RUN_TIME := 880us
+
+include $(VHDL_HOME)/make/ghdl.mk
+# -----------------------------------------------------------
+
diff --git a/lib/uart/ghdl/uart_sim.inc b/lib/uart/ghdl/uart_sim.inc
new file mode 100644
index 0000000..0ca72b2
--- /dev/null
+++ b/lib/uart/ghdl/uart_sim.inc
@@ -0,0 +1,13 @@
+# -----------------------------------------------------------
+include $(VHDL_HOME)/make/defs.mk
+# -----------------------------------------------------------
+PKG_NAME := UART_SIM
+
+# -----------------------------------------------------------
+MOD_PATH := $(LIB_PATH)/uart/src
+
+$(PKG_NAME)_SRCS += $(MOD_PATH)/uart_types.vhd
+$(PKG_NAME)_SRCS += $(MOD_PATH)/sim/uart.vhd
+
+# -----------------------------------------------------------
+