diff --git a/lib/CPUs/MIPS/src/core/dcache.vhd b/lib/CPUs/MIPS/src/core/dcache.vhd
index c70bc47..65087cc 100644
--- a/lib/CPUs/MIPS/src/core/dcache.vhd
+++ b/lib/CPUs/MIPS/src/core/dcache.vhd
@@ -175,22 +175,35 @@ END COMPONENT;
 	signal	was_miss				: std_logic;
 	signal	data_write				: std_logic;
 	signal	cpu_we2					: std_logic;
+	signal	cpu_hit_we				: std_logic;
+	signal	instant_raw				: std_logic;
 
 begin
 
+	cpu_hit_we	<= cpu_we2 and not cache_write_miss;
 	
-cpu_index_reg:
+cpu_index_register:
 	process(CLK_I)
 	begin
 		if rising_edge(CLK_I) then
 			if RST_I = '1' then
 				cache_index_reg	<= (others => '0');
 				tag_index_reg	<= (others => '0');
-				cpu_was_write	<= '0';
-			elsif cpu_reg_en = '1' and en = '1' then
+			elsif cpu_reg_en = '1' and en = '1' and instant_raw = '0' then
 				word_index_reg	<= cpu_word_index;
 				cache_index_reg	<= cpu_cache_index;
 				tag_index_reg	<= cpu_tag;
+			end if;
+		end if;
+	end process;	
+
+cpu_data_register:
+	process(CLK_I)
+	begin
+		if rising_edge(CLK_I) then
+			if RST_I = '1' then
+				cpu_was_write	<= '0';
+			elsif cpu_reg_en = '1' and en = '1' then
 				cpu_data_reg	<= cpu_din;
 				cpu_we_reg		<= cpu_we;
 				cpu_was_write	<= not cpu_r_wn;
@@ -198,7 +211,7 @@ cpu_index_reg:
 		end if;
 	end process;	
 
-cpu_was_wr_reg:
+cpu_was_wr_register:
 	process(CLK_I)
 	begin
 		if rising_edge(CLK_I) then
@@ -212,6 +225,14 @@ cpu_was_wr_reg:
 		end if;
 	end process;	
 
+instant_raw_logic:
+	process(CLK_I)
+	begin
+		if rising_edge(CLK_I) then
+			instant_raw	<= cpu_hit_we and cpu_en and en and cpu_r_wn;
+		end if;
+	end process;	
+
 inst_tag_ram : dpram_1w1r
 	GENERIC MAP (
 		addr_width	=> tram_addr_width,
@@ -266,7 +287,7 @@ cache_state_next:
 		end if;
 	end process;	
 
-	cpu_busy			<= cache_busy;
+	cpu_busy			<= cache_busy or instant_raw;
 	cpu_dout			<= cpu_dram_dout;
 	
 	tag_match			<= '1' when tag_index_reg = cache_entry_out.tag else '0';
@@ -275,15 +296,15 @@ cache_state_next:
 	tram_din			<= to_tram_data(cache_entry_in);
 	tram_addr_rd		<= cpu_cache_index when was_miss = '0' else cache_index_reg;
 	cache_entry_out		<= to_dcache_entry(tram_dout);
-	cpu_dram_addr		<= (cpu_cache_index & cpu_word_index) when (was_miss = '0' and cpu_we2 = '0') else (cache_index_reg & word_index_reg);
+	cpu_dram_addr		<= (cpu_cache_index & cpu_word_index) when (was_miss = '0' and cpu_hit_we = '0' and instant_raw = '0') else (cache_index_reg & word_index_reg);
 	ADDR_O				<= tag_index_reg & cache_index_reg & to_unsigned(mem_index_count, word_index_width) & "00";
 	ctrl_dram_addr		<= cache_index_reg & to_unsigned(ram_index_count, word_index_width);
 	ctrl_dram_din		<= DAT_I;
 	ctrl_dram_we		<= (3 downto 0 => (data_write and ACK_I)) or ctrl_force_we;
-	cpu_dram_we			<= cpu_we_reg when (cpu_we2 = '1' and cache_write_miss = '0') else (others => '0');
+	cpu_dram_we			<= cpu_we_reg when (cpu_hit_we = '1') else (others => '0');
 	
 cache_state:
-	process(s, cache_read_miss, cache_index_count, ram_index_count, mem_index_count, cache_index_reg, ACK_I, tag_index_reg, cpu_en, cpu_r_wn, SRDY_I, cpu_was_en, cpu_was_write, cpu_we_reg)
+	process(s, instant_raw, cache_read_miss, cache_index_count, ram_index_count, mem_index_count, cache_index_reg, ACK_I, tag_index_reg, cpu_en, cpu_r_wn, SRDY_I, cpu_was_en, cpu_was_write, cpu_we_reg)
 	begin
 		cpu_reg_en				<= '0';
 		cache_busy 				<= '1';